Professor, School of Computing
Ph.D., University of Utah, 1972
Professor Davis joined the faculty in 1993. His
research interests involve high performance computer architectures and
digital system design methodologies. More specifically he is
interested in parallel processor architectures, high performance
uniprocessor I/O architecture, VLSI, VLSI CAD, high performance
communication, and asynchronous circuits. Prior to his joining the
faculty in the fall of 1993, he spent the previous 12 years as a
research scientist working on the design and implementation of
parallel processing systems at Schlumberger Palo Alto Research and
subsequently at Hewlett-Packard Laboratories. Recent accomplishments
include 1) the development of an automatic asynchronous circuit
synthesis system called STETSON; 2) the design and implementation of
an asynchronous scalable parallel communication fabric VLSI component
called FEDEX which is capable of supporting 500 MB/sec sustained
bandwidth on each of its 7 ports; and 3) the development of an
extensible and scalable parallel processing system called MAYFLY and
4) the development of a very low latency message passing protocols
called Direct Deposit. He is currently involved in the DARPA
sponsored Impulse project (Prof. John Carter is the PI) which is
developing an adaptive memory controller that is capable of
dynamically organizing cache lines to suit the applications needs.
During the 1999-2000 academic year, Professor Davis was on sabbatical
at Intel in Austin, Texas where he lead the I/O and memory
architecture efforts for the IA32 processor which is expected to be in
production in 2003.