Professor, School of Computing
Ph.D., University of Utah, 1972
Professor Davis joined the faculty in 1993. His
research interests involve high performance computer architectures
and digital system design methodologies. More specifically he is
interested in parallel processor architectures, high performance
uniprocessor I/O architecture, VLSI, VLSI CAD, high performance communication, and
asynchronous circuits. Prior to his joining the faculty in the fall of
1993, he spent the previous 12 years as a research scientist working on the
design and implementation of parallel processing systems at Schlumberger
Palo Alto Research and subsequently at Hewlett-Packard Laboratories.
Recent accomplishments include 1) the development of an automatic
asynchronous circuit synthesis system called STETSON; 2) the design and
implementation of an asynchronous scalable parallel communication fabric
VLSI component called FEDEX which is capable of supporting 500 MB/sec
sustained bandwidth on each of its 7 ports; and 3) the development of an
extensible and scalable parallel processing system called MAYFLY and 4) the
devolopment of a very low latency message passing protocols called
Direct Deposit. He is currently involved in the DARPA sponsored Impulse
project (Prof. John Carter is the PI) which is developing an adaptive
memory controller that is capable of dynamically organizing cache lines
to suit the applications needs. During the 1999-2000 academic year,
Professor Davis will be on sabbatical at Intel in Austin, Texas where he
is leading the I/O and memory architecture efforts for the IA32 processor
which is expected to be in production in 2003.
- J. Carter, W. Hsieh, L. Stoller, M. Swanson, L. Zhang, E. Brunvand,
A. Davis, C.-C. Kuo, R. Kuramkote, M. Parker, L. Schaelicke, and
T. Tateyama. Impulse: Building a Smarter Memory Controller. Proceedings
of the Fifth International Symposium on High Performance Computer
Architecture, pp. 70-79, January 1999.
- L. Schaelicke and A. Davis. Improving I/O Performance with a
Conditional Store Buffer. Proceedings of the 31st Annual ACM/IEEE
International Symposium on Microarchitecture, pp. 160-169, November 1998.
- A. Davis, M. Swanson, M. Parker. Efficient Communication Mechanisms
for Cluster Based Parallel Computing. Springer-Verlag Lecture Notes
in Computer Science #1199. Feb. 1997, pp. 1-15.
- A. Davis. Asynchronous Digital Circuit
Design. Chapter 3: `Synthesizing Asynchronous Circuits: Practice and
Experience'. Springer-Verlag Workshops in Computing series, April 1995,
pp. 104 - 151.
- A. Davis. R2 - A Damped Adaptive Router Design.
Parallel Computer Routing and Communication. Springer-Verlag Lecture Notes
in Computer Science #853. May 1994, pp. 295-309.
- A. Davis. Mayfly: A General-Purpose, Scalable, Parallel Processing
Architecture. Lisp and Symbolic Computation, Volume 5, Numbers 1/2,
May 1992, pp. 7-47.