Professor of Computer Science
Ph.D., University of Utah, 1972
Professor Davis joined the Department in 1993. His
research interests include convergence parallel processing system
architectures, VLSI, VLSI CAD, high performance communication, and
asynchronous circuits. Prior to his joining the faculty in the fall of
1993, he spent the previous 12 years as a research scientist working on the
design and implementation of parallel processing systems at Schlumberger
Palo Alto Research and subsequently at Hewlett-Packard Laboratories.
Recent accomplishments include 1) the development of an automatic
asynchronous circuit synthesis system called STETSON; 2) the design and
implementation of an asynchronous scalable parallel communication fabric
VLSI component called FEDEX which is capable of supporting 500 MB/sec
sustained bandwidth on each of its 7 ports; and 3) the development of an
extensible and scalable parallel processing system called MAYFLY which
contains 19 processing elements and has to date exhibited scalable
performance for a wide range of business and scientific applications.
Current research interests include the development of low-latency
communication protocols and network interface hardware (supported by
Hewlett Packard), the design of a scalaable parallel processor which
supports flexible distributed shared memory and low-latency message passing
programming models (supported by ARPA), and a novel adaptive memory system
(supported by ARPA).
