University of Utah
Department of Computer Science
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Professor of Computer Science
Ph.D.
, University of Utah, 1972
Professor Davis
joined the Department in 1993. His research
interests include shared nothing parallel processing system architecture, VLSI,
VLSI CAD, and asynchronous circuits. Prior to his joining the faculty in the
fall of 1993, he has spent the previous 11 years as a research scientist
working on the design and implementation of parallel processing systems at
Schlumberger Palo Alto Research and subsequently at Hewlett-Packard
Laboratories. Recent accomplishments include 1) the development of an
automatic asynchronous circuit synthesis system called STETSON; 2) the design
and implementation of an asynchronous scalable parallel communication fabric
VLSI component called FEDEX which is capable of supporting 500 MB/sec sustained
bandwidth on each of its 7 ports; and 3) the development of an extensible and
scalable parallel processing system called MAYFLY which contains 19 processing
elements and has to date exhibited scalable performance for a wide range of
business and scientific applications. Current research interests include the
development of low-latency communication protocols and network interface
hardware (supported by Hewlett Packard) and the design of a novel memory
system architecture for parallel computing (supported by ARPA).
- A. Davis. Asynchronous Digital Circuit
Design. Chapter 3: `Synthesizing Asynchronous Circuits: Practice and
Experience'. Springer-Verlag Workshops in Computing series, April 1995,
pp. 104 -- 151.
- Al Davis, L. Cherkasova, Vadim Kotov, Tomas Rokicki
Colored Petri Net Methods for Performance Analysis of
Scalable High-Speed Interconnects. Proceedings of International
Workshop on Modeling, Analysis and Simulation of Computer and
Telecommunication Systems (MASCOTS'94), 1994.
- A. Davis. R2 - A Damped Adaptive Router Design.
Parallel Computer Routing and Communication. Springer-Verlag Lecture Notes
in Computer Science #853. May 1994, pp. 295-309.
- A. Davis, B. Coates, K. Stevens. The Post Office Experience:
designing a large asynchronous chip. Integration Vol. 15, No. 3,
November 1993, pp. 341-366.
- A. Davis. Mayfly: A General-Purpose, Scalable, Parallel Processing
Architecture. Lisp and Symbolic Computation, Volume 5, Numbers 1/2,
May 1992, pp. 7--47.
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Next: Ganesh C. Gopalakrishnan
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