Distinguished Lecture Series
Norm Jouppi
HP Labs
Wednesday, March 7, 2012
1230 WEB
Refreshments 3:20 p.m.
Lecture 3:40 p.m.
Host: Rajeev Balasubramonian
Title: Future Computer Technologies and Their Architectural Implications
Norm Jouppi
HP Labs
Wednesday, March 7, 2012
1230 WEB
Refreshments 3:20 p.m.
Lecture 3:40 p.m.
Host: Rajeev Balasubramonian
Title: Future Computer Technologies and Their Architectural Implications
Abstract
We believe the scaling of computer technologies will not come to an abrupt simultaneous end, but as time progresses more and more component technologies will reach their limits and need to be replaced or augmented with new technologies. Some of these new technologies are relatively straightforward replacements from an architecture and systems standpoint; however others will have more disruptive architectural implications. For example, the adoption of high-K gate dielectrics and fin-FET transistors should have limited implications for systems architecture (other than giving them better performance and power efficiency). In contrast, 3D die stacking, advances in optical interconnects, and emerging non-volatile memory technologies are likely to have more disruptive effects on system architecture. For instance, new non-volatile memory technologies are promising much better scalability, endurance, and access speeds than disks or flash drives. Combined with slower disk scaling, many applications will soon be able to switch to mostly in-memory processing. Similarly, optical interconnects are becoming useful at shorter distance scales and can enable the use of more complex interconnect topologies such as busses and crossbars, rather than being limited to point-to-point links like high speed electrical interconnects. In this talk we describe recent technology developments and our architecture research at HP leveraging these opportunities.
BIO
Norman P. Jouppi is an HP Senior Fellow and Director of the Intelligent Infrastructure Lab at HP Labs. He is known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area, and power. He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence. Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, where he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification. He currently serves on the boards of the Computing Research Association (CRA) and ACM SIGARCH. He is on the editorial board of Communications of the ACM and IEEE Micro. He is a Fellow of the ACM and the IEEE, and holds more than 60 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.
We believe the scaling of computer technologies will not come to an abrupt simultaneous end, but as time progresses more and more component technologies will reach their limits and need to be replaced or augmented with new technologies. Some of these new technologies are relatively straightforward replacements from an architecture and systems standpoint; however others will have more disruptive architectural implications. For example, the adoption of high-K gate dielectrics and fin-FET transistors should have limited implications for systems architecture (other than giving them better performance and power efficiency). In contrast, 3D die stacking, advances in optical interconnects, and emerging non-volatile memory technologies are likely to have more disruptive effects on system architecture. For instance, new non-volatile memory technologies are promising much better scalability, endurance, and access speeds than disks or flash drives. Combined with slower disk scaling, many applications will soon be able to switch to mostly in-memory processing. Similarly, optical interconnects are becoming useful at shorter distance scales and can enable the use of more complex interconnect topologies such as busses and crossbars, rather than being limited to point-to-point links like high speed electrical interconnects. In this talk we describe recent technology developments and our architecture research at HP leveraging these opportunities.
BIO
Norman P. Jouppi is an HP Senior Fellow and Director of the Intelligent Infrastructure Lab at HP Labs. He is known for his innovations in computer memory systems, including stream prefetch buffers, victim caching, multi-level exclusive caching and development of the CACTI tool for modeling cache timing, area, and power. He has also been the principal architect and lead designer of several microprocessors, contributed to the architecture and design of graphics accelerators, and extensively researched video, audio, and physical telepresence. Jouppi received his Ph.D. in electrical engineering from Stanford University in 1984, where he was one of the principal architects and designers of the MIPS microprocessor, as well as a developer of techniques for CMOS VLSI timing verification. He currently serves on the boards of the Computing Research Association (CRA) and ACM SIGARCH. He is on the editorial board of Communications of the ACM and IEEE Micro. He is a Fellow of the ACM and the IEEE, and holds more than 60 U.S. patents. He has published over 100 technical papers, with several best paper awards and one Symposium on Computer Architecture (ISCA) Influential Paper Award.