Abstract
Modern computer architectures are undergoing a paradigm shift, where every microprocessor, from embedded to desktop to supercomputing socket, will be a parallel "multi-core" architecture. New architectural features ushered in by the multi-core era include shared caches, software-managed storage, SIMD compute engines and heterogeneous processor hierarchies. At the same time, applications have also continued on their trajectory of increasing complexity, with large teams, mixed languages, and significant reuse of existing software. All this added architecture and application complexity poses enormous challenges for software developers in obtaining acceptable levels of performance. Even maintaining current levels of performance on new architectures is threatened.

In this talk, we discuss the role of compiler technology in managing this complexity by providing the support essential to exploit the unique performance-enhancing features offered by target architectures while freeing programmers from managing low-level details. The overall research goal is to develop a systematic and principled approach to automatic and semi-automatic performance tuning of key computations in applications. We examine the very structure of today's compilers, which are currently difficult to retarget to new architectures, and propose a systematic and principled strategy to architecture-specific optimization. Based on scenarios from our work with library developers and application scientists, we describe how this compiler technology can enable programmers to achieve the same or better performance results, sometimes comparable to hand-tuned performance, in a much more productive way.