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Colloquium

Manish Vachharajani
Department of Electrical and Computer Engineering
University Colorado at Boulder

Tuesday, November 4, 2008
3105 MEB
Lecture 12:05 p.m.

Host: Ganesh Gopalakrishnan


Title: Visualizing Potential Parallelism in Sequential Programs

Abstract
This talk will presents ParaMeter, an interactive program analysis and visualization system for large traces. Using ParaMeter, a software developer can locate and analyze regions of code that may yield to parallelization efforts and to possibly extract performance from multicore hardware. The key contributions in the paper are (1) a method to use interactive visualization of traces to find and exploit parallelism, (2) interactive-speed visualization of large-scale trace dependencies, (3) interactive-speed visualization of code interactions, and (4) a BDD variable ordering for BDD-compressed traces that results in fast visualization, fast analysis, and good compression. ParaMeter's effectiveness is demonstrated by finding and exploiting parallelism in 175.vpr. Measurements of ParaMeter's visualization algorithms show that they are up to seventy-five thousand times faster than prior approaches.

Bio
Manish Vachharajani is an assistant professor in the Department of Electrical and Computer Engineering at the University of Colorado at Boulder. His research is focused on programming and design of advanced multicore systems ranging from general purpose homogeneous multicores to special purpose compute platforms such as GPUs. Current results from his group range from record-breaking network-processing performance on commodity multicore hardware to substantial speedups of industrial strength numerical weather prediction codes.

Manish completed his Ph.D. at Princeton University in 2004. His dissertation describes techniques for rapid specification of accurate processor models; these techniques are the cornerstone of the Liberty Simulation Environment (LSE), a publicly available modeling tool. Manish has also studied compiler techniques for automatic retargetability, compiler techniques for microarchitecture specific optimization, and processor architectures for performance.

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