CMP-MSI: 2nd Workshop on Chip Multiprocessor Memory Systems and Interconnects

In conjunction with the

35th International Symposium on Computer Architecture (ISCA-35)

Sunday, June 22nd, 2008
Beijing, China

Scope:

The fact that now these components will be tightly integrated onto the same die presents opportunities and challenges that are very different than those that existed in previous multi-processor systems. This workshop aims to become a forum for academia and industry to discuss and present ideas and recent developments in the design and evaluation of on-chip multiprocessor memory systems and interconnects.

Tentative Program:

Caching: 8:00 am - 9:20 am

• Dynamic Parameter Tuning for Hardware Prefetching Using Shadow Tagging , Marius Grannaes and Lasse Natvig, Norwegian University of Science and Technology.
• Double-DIP: Augmenting DIP with Adaptive Promotion Policies to Manage Shared L2 Caches , Jonathan D. Kron, Brooks Prumo, Gabriel H. Loh, Georgia Institute of Technology.
• Extending the Scalability of Single Chip Stream Processors with On-chip Caches , Ali Bakhoda and Tor M. Aamodt, University of British Columbia.
• Dynamic Classification of Program Memory Behaviors in CMPs , Yuejian Xie, Gabriel H. Loh, Georgia Institute of Technology.

Keynote: 9:30 am - 10:15 am

• Per Stenstrom, Chalmers University of Technology
  Scalability Issues for Future Chip Multiprocessors

  Abstract: Computer industry has embraced multi-cores as a contingency plan for the challenging problems associated with scaling up superscalar processors to higher single-thread performance. However, moving along the multi-core roadmap has its challenges. A first challenge is how we can provide the right architectural support to expose a more productive interface to the software. A second challenge concerns how we can provide the cores with a scalable memory bandwidth and a short latency time to the memory within technological constraints. This talk will review some approaches that are currently under investigation and present some views on where I think we should be headed.

  The European Commision is currently supporting multiple projects that address these challenges. SARC (Scalable Computer Architecture) is a project whose objective is to provide a scalability path for multi-cores by addressing issues all across the system stack. I will end this task by providing an overview of the current status of the SARC project.

  Bio: Prof. Per Stenstrom is a professor of computer engineering at Chalmers University of Technology. His research interests are devoted to design principles for high-performance computer systems. He is an author of two textbooks and more than a hundred research publications. He is regularly serving program committees of major conferences in the computer architecture field. He has been an editor of IEEE Transaction on Computers, is an editor of Journal of Parallel and Distributed Computing, the IEEE TCCA Computer Architecture Letters, and a founding editor-in-chief of the Journal of High-Performance Embedded Architectures and Compilation Techniques. He has served as General as well as Program Chair of the ACM/IEEE International Symposium on Computer Architecture. He is a Fellow of the IEEE and member of ACM.

Interconnects: 10:30 am - 11:05 am

• Scalable On-Chip Interconnect Topologies , Boris Grot and Stephen W. Keckler, The University of Texas at Austin.
• Position paper: Ultraperformance Wireless Interconnect Nanonetworks for Heterogeneous Gigascale Multi-Processor SoCs , Danella Zhao, University of Louisiana.

Coherence: 11:15 am - 12:10 pm

• Position Paper: Architecture Supported Synchronization-Based Cache Coherence Protocol For Many-Core Processors , He Huang, Nan Yuan, Wei Lin, Guoping Long, Fenglong Song, Lei Yu, Yuping Liu, Lei Liu, Yongbin Zhou, Xiaochun Ye, Junchao Zhang, Dongrui Fan, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China.
• Alternative Home: Balancing Distributed CMP Coherence Directory , Zhuo Huang (University of Florida), Xudong Shi (Google Inc.), Ye Xia (University of Florida), Jih-Kwon Peir (University of Florida).
• Perceptron-based Coherence Predictors , Devyani Ghosh, John B. Carter, Hal Daume III, University of Utah.

Call for Papers (deadline has passed):

1. Technical papers (at least 6 pages) for relatively mature ideas.
2. Position papers (3 pages maximum) on directions for research and development.

The selected papers will be made available online. However, publication in CMP-MSI does not preclude later publication at regular conferences or journals. Some papers may be nominated for inclusion in a "Best of ISCA 2008 Workshops" special issue journal publication.

Topics of interest include:

• Memory system design and optimizations
• Interconnect design and optimizations
• Policies for non-uniform cache access (NUCA) and shared/private caching
• 3D stacked cache hierarchies
• Improvements to cache hierarchy and interconnect power, temperature, reliability, security, and complexity
• Coherence optimizations
• Memory system support for alternative execution models such as transactional memory
• Memory and interconnect designs for heterogeneous CMP architectures where some of the computation cores are specialized (e.g., GPUs)
• Support for software optimizations and or enhanced functionality (e.g., debugging, tracing, checkpointing)
• Early reports on system prototypes

Important Dates

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