CMP-MSI: 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects
In conjunction with the
Saturday, June 20th, 2009
Austin, Texas, USA
Tentative Program
1:30pm: Keynote
- Multicore Processors for the Next Decade, Antonio Gonzalez , Intel Barcelona Research Center and UPC.
Abstract
Moore's law has fueled a dramatic evolution in microprocessor and will keep doing it in forthcoming generations. Microprocessor designers have leveraged the improvements in process technology to enhance the microarchitecture of processors in different manners. In this quest for delivering higher performance, the whole industry has recently started a journey in the land of multicores. Multicores are very effective to increase computing density, by increasing the number of processing units generation after generation.
The scalability of multicore processors faces multiple challenges that will require significant innovation in applications, programming paradigms and tools, and architectures. In this talk, I will describe some of the research avenues that are being pursued to address these challenges.
2:15pm - 3:15pm: Session 1
- An Intra-Chip Free-Space Optical Interconnect , Jing Xue, Alok Garg, Berkehan Ciftcioglu, Shang Wang, Ioannis Savidis, Jianyun Hu, Manish Jain, Michael Huang, Hui Wu, Eby G. Friedman, Gary W. Wicks, Duncan Moore (University of Rochester).
- Comparison of Physical Express Topologies and Virtual Express Topologies for future Many-core On-Chip Networks , Chia-Hsin
Owen Chen (Princeton), Niket Agarwal (Princeton), Tushar Krishna
(Princeton), Kyung-Hoae Koo (Stanford), Li-Shiuan Peh (Princeton),
Krishna C. Saraswat (Stanford).
3:30pm-5pm: Session 2
- Soft Coherence: Preliminary Experiments with Error-Tolerant Memory Consistency in Numerical Applications , Fred Chong (UCSB), Diana Franklin (UCSB), John Gilbert (UCSB), Guoping Long (Chinese Academy of Sciences), Dongrui Fan (Chinese Academy of Sciences).
- History-Aware, Resource-Based Dynamic Scheduling for Heterogeneous Multi-core Processors , Ali Jooya (Iran University of Science and Technology), Amirali Baniasadi (University of Victoria), Morteza Analoui (Iran University of Science and Technology).
- Design Enhancements for In-Cache Computations , Patrick A. La Fratta, Peter M. Kogge (University of Notre Dame).