CMP-MSI: 3rd Workshop on Chip Multiprocessor Memory Systems and Interconnects
In conjunction with the
Saturday, June 20th, 2009
Austin, Texas, USA
Scope:
Chip multiprocessors (CMPs or multi-cores) are emerging as the architecture
of choice for future high performance processors. CMPs integrate several
high-performance processing cores onto the same chip. A high performance
interconnect and memory system are necessary to satisfy the data
supply needs of all these cores especially given the ever increasing
speed gap between processors and main memory systems. At the same
time, power, complexity, and reliability are additional constraints
that must be met by any design. We also recognize that for multi-cores
to be successful, advancements must be made in the area of semi- or
full-automatic parallelization of applications. This year, we would
therefore like to emphasize submissions that deal with the implications
of semi- or full-automatic parallelization on memory systems and
interconnect.
Call for Papers:
Two kinds of papers are invited:
- Technical papers (at least 6 pages) for relatively mature ideas.
- Position papers (3 pages maximum) on directions for research and development.
Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font. Please submit an abstract (less than 300 words) a week before the paper submission deadline. Paper submissions will be accepted through May 1 even if an abstract was not submitted early. Submission site . For questions regarding the submission site, please send email
to the Web Chair .
The selected papers will be made available online. However,
publication in CMP-MSI does not preclude later publication at regular
conferences or journals.
Topics of interest include:
- Memory system design and optimizations
- Interconnect design and optimizations
- Policies for non-uniform cache access (NUCA) and shared/private caching
- 3D stacked cache hierarchies
- Improvements to cache hierarchy and interconnect power, temperature,
reliability, security, and complexity
- Coherence optimizations
- Memory system support for alternative execution models such as
transactional memory
- Impact of interconnect and memory on the performance and ease of
parallel programming models/environments
- Memory and interconnect designs for heterogeneous CMP architectures
where some of the computation cores are specialized (e.g., GPUs)
- Support for software optimizations and or enhanced functionality
(e.g., debugging, tracing, checkpointing)
- Early reports on system prototypes
Important Dates
Abstract due (optional): Friday April 24, 2009
Paper Due: Friday May 1, 2009
Notification: Tuesday May 19, 2009
Final Paper Due: Tuesday May 26, 2009
Submission site
Organizers
Rajeev Balasubramonian , University of Utah
Andreas Moshovos , University of Toronto
Yiannakis Sazeides , University of Cyprus
Web Chair
Naveen Muralimanohar , University of Utah
Program Committee
Mani Azimi, Intel
Rajeev Balasubramonian, Univ. of Utah
Francois Bodin, CAPS Enterprise
Mainak Chaudhuri, IIT Kanpur
Ravishankar Iyer, Intel
Natalie Enright Jerger, Univ. of Toronto
Babak Falsafi, EPFL/CMU
John Kim, Northwestern University
Andreas Moshovos, Univ. of Toronto
Yiannakis Sazeides, Univ. of Cyprus
Andre Seznec, Irisa/INRIA
Viji Srinivasan, IBM TJ Watson
Jun Yang, Univ. of Pittsburgh
Previous Workshops
CMP-MSI 2008
CMP-MSI 2007