Final Program

• Bulk Multicore, Josep Torrellas , UIUC.
  Abstract: One of the biggest challenges facing computer architecture today is the design of parallel architectures that efficiently support a highly-programmable environment. In this talk, I will present the Bulk Multicore Architecture, an architecture that is highly programmable, while delivering high performance and keeping the hardware simple. The Bulk Multicore is based on the idea of eliminating the commit of individual instructions. It supports sequential consistency and offers substantial advantanges for new software environments and new tool development. I will discuss the ongoing architecture, compilation, and tool efforts.
  
  Bio: Josep Torrellas is a Professor and Willett Faculty Scholar at the University of Illinois. Prior to being at Illinois, Torrellas received a PhD from Stanford University. He also spent a year at IBM's T.J. Watson Research Center. Torrellas's research area is multiprocessor computer architecture. He leads the Illinois Aggressive COMA Multiprocessor group. He has been involved in the Stanford DASH and the Illinois Cedar multiprocessor projects, and contributed extensively in the area of shared-memory multiprocessor architecture and thread-level speculation. He received several best-paper awards. He is an IEEE Fellow.

2:10pm - 3:00pm: Session 1 , Chair: S. Murali

• 2:10-2:30pm Realistic Workload Characterization and Analysis for Networks-on-Chip Design , Paul V. Gratz (Texas A&M University), Stephen W. Keckler (University of Texas at Austin).
• 2:30-2:50pm Decoupled Zero-Compressed Memory , Julien Dusser, Andre Seznec (INRIA/IRISA).
• 2:50-3:00pm The Case for Coherence-less Distributed Cache Architecture , Andras Vajda (Ericsson).

3:00-3:30pm: Coffee Break

3:30-4:10pm: Session 2 , Chair: R. Balasubramonian

• 3:30-3:50pm Understanding the Limits of Capacity Sharing in CMP Private Caches , Ahmad Samih (NCSU), Anil Krishna (IBM), Yan Solihin (NCSU).
• 3:50-4:10pm Using Dead Blocks as a Virtual Victim Cache , Samira Khan (University of Texas at San Antonio), Daniel Jimenez (University of Texas at San Antonio), Doug Burger (Microsoft Research), Babak Falsafi (EPFL).
• Hardware Assisted Resource Sharing Platform for Personal Cloud , Wei Wang, Ya Zhang, Xuezhao Liu, Meilin Zhang, Xiaoyan Dang, Zhuo Wang (Intel).

4:15-5:00pm: Panel

• How do we Scale the Bandwidth Wall?
  Panelists: John Kim (KAIST), Hsien-Hsin (Sean) Lee (GaTech), Andre Seznec (IRISA/INRIA), Yan Solihin (NCSU).
  Moderator: P. Kundu
  Thanks to Moore's law, we expect to have unprecedented compute density in future multi-core CPUs and GPUs. However, the scaling of pin bandwidth has been much more modest, creating an imminent memory bottleneck in future CMPs. Researchers have previously proposed innovative solutions including 3D stacking, multi-die packaging, clever bandwidth and cache allocation schemes, novel memory systems - much of this supported by the next generation of on and off die interconnection solutions. This panel will discuss a multi-pronged approach to tackling the bandwidth issue.
  

Scope:

Call for Papers:

1. Technical papers (at least 6 pages) for relatively mature ideas.
2. Position papers (3 pages maximum) on directions for research and development.

The selected papers will be made available online. However, publication in CMP-MSI does not preclude later publication at regular conferences or journals.

Topics of interest include:

• Novel memory and interconnect architectures for many-core CPUs and SoCs
• Memory system architecture for specialized multi-core chips for gaming, networking, media, financial and scientific applications
• Interconnect design and optimizations
• Policies for non-uniform cache access (NUCA) and shared/private caching
• 3D stacked cache hierarchies
• Improvements to cache hierarchy, power, reliability, security and complexity
• Coherence optimizations
• Impact of interconnect and memory on the performance and ease of parallel programming models/environments
• Support for software optimizations and/or enhanced functionality (e.g., debugging, tracing, check pointing)
• Workload characteristics of SoCs with special emphasis on memory interfaces and memory access
• Communication protocols between cores, caches and accelerators
• Early reports on system prototypes

Important Dates

Submission site

Organizers

Web Chair

Program Committee

Previous Workshops

CMP-MSI 2008

CMP-MSI 2007