CMP-MSI: 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects
In conjunction with the
Saturday, January 9th, 2010
- Bulk Multicore, Josep Torrellas , UIUC.
One of the biggest challenges facing computer architecture
today is the design of parallel architectures that efficiently
support a highly-programmable environment. In this talk,
I will present the Bulk Multicore Architecture, an architecture
that is highly programmable, while delivering high performance
and keeping the hardware simple. The Bulk Multicore is
based on the idea of eliminating the commit of individual
instructions. It supports sequential consistency and
offers substantial advantanges for new software environments
and new tool development. I will discuss the ongoing architecture,
compilation, and tool efforts.
Josep Torrellas is a Professor and
Willett Faculty Scholar at the University of Illinois. Prior to
being at Illinois, Torrellas received a PhD from Stanford University.
He also spent a year at IBM's T.J. Watson Research Center. Torrellas's
research area is multiprocessor computer architecture.
He leads the Illinois Aggressive COMA Multiprocessor group. He
has been involved in the Stanford DASH and the Illinois Cedar
multiprocessor projects, and contributed extensively in the
area of shared-memory multiprocessor architecture and
thread-level speculation. He received several best-paper
awards. He is an IEEE Fellow.
2:10pm - 3:00pm: Session 1 , Chair: S. Murali
3:00-3:30pm: Coffee Break
3:30-4:10pm: Session 2 , Chair: R. Balasubramonian
- 3:30-3:50pm Understanding the Limits of Capacity Sharing in CMP Private Caches , Ahmad Samih (NCSU), Anil Krishna (IBM), Yan Solihin (NCSU).
- 3:50-4:10pm Using Dead Blocks as a Virtual Victim Cache , Samira Khan (University of Texas at San Antonio), Daniel Jimenez (University of Texas at San Antonio), Doug Burger (Microsoft Research), Babak Falsafi (EPFL).
- Hardware Assisted Resource Sharing Platform for Personal Cloud , Wei Wang, Ya Zhang, Xuezhao Liu, Meilin Zhang, Xiaoyan Dang, Zhuo Wang (Intel).
- How do we Scale the Bandwidth Wall?
Panelists: John Kim (KAIST), Hsien-Hsin (Sean) Lee (GaTech), Andre Seznec (IRISA/INRIA), Yan Solihin (NCSU).
Moderator: P. Kundu
Thanks to Moore's law, we expect to have unprecedented compute density in
future multi-core CPUs and GPUs. However, the scaling of pin bandwidth has been
much more modest, creating an imminent memory bottleneck in future CMPs.
Researchers have previously proposed innovative solutions including 3D stacking,
multi-die packaging, clever bandwidth and cache allocation schemes, novel
memory systems - much of this supported by the next generation of on and off
die interconnection solutions. This panel will discuss a multi-pronged approach
to tackling the bandwidth issue.
Chip multiprocessors (CMPs) have emerged as the architecture of choice in both general purpose processors as
well as in embedded systems. Modern CMPs integrate several high-performance processing cores as well as
accelerators onto the same chip. A high performance interconnect and memory system is necessary to satisfy the
data supply needs of all the processing units, especially given the ever increasing speed gap between processors
and main memory systems. This year, emphasis will be given to the memory needs of on-board fixed function
units/accelerators and exploration of suitable memory and interconnect architectures.
This workshop aims to remain a premier forum for academia and industry to discuss and present ideas related to
architecture, design and evaluation of on-chip multiprocessor memory systems and interconnects.
Call for Papers:
Two kinds of papers are invited:
Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font. Please submit an abstract (less than 300 words) a week before the paper submission deadline. Paper submissions will be accepted through Nov 10th even if an abstract was not submitted early. Submission site . For questions regarding the submission site, please send email
to the Web Chair .
- Technical papers (at least 6 pages) for relatively mature ideas.
- Position papers (3 pages maximum) on directions for research and development.
The selected papers will be made available online. However,
publication in CMP-MSI does not preclude later publication at regular
conferences or journals.
Topics of interest include:
- Novel memory and interconnect architectures for many-core CPUs and SoCs
- Memory system architecture for specialized multi-core chips for gaming, networking, media, financial and scientific applications
- Interconnect design and optimizations
- Policies for non-uniform cache access (NUCA) and shared/private caching
- 3D stacked cache hierarchies
- Improvements to cache hierarchy, power, reliability, security and complexity
- Coherence optimizations
- Impact of interconnect and memory on the performance and ease of parallel programming models/environments
- Support for software optimizations and/or enhanced functionality
(e.g., debugging, tracing, check pointing)
- Workload characteristics of SoCs with special emphasis on memory interfaces and memory access
- Communication protocols between cores, caches and accelerators
- Early reports on system prototypes
Abstract due (optional): Monday November 2, 2009
Paper Due: Monday November 9, 2009
Notification: Monday November 23, 2009
Final Paper Due: Monday December 14, 2009
Mani Azimi, Intel Labs
Rajeev Balasubramonian , University of Utah
Partha Kundu , Intel Labs
David Nellans , University of Utah
Dave Albonesi, Cornell
Mani Azimi, Intel Labs
Rajeev Balasubramonian, Univ. of Utah
Davide Bertozzi, Univ. of Ferrara
Mainak Chaudhuri, IIT Kanpur
Sangyeun Cho, Univ. of Pittsburgh
Natalie Enright Jerger, Univ. of Toronto
Yuho Jin, USC
Anshul Kumar, IIT Delhi
Partha Kundu, Intel Labs
Andreas Moshovos, Univ. of Toronto
Naveen Muralimanohar, HP Labs
Li-Shiuan Peh, MIT
Yiannakis Sazeides, Univ. of Cyprus
Andre Seznec, Irisa/INRIA
Li Shang, Univ. of Colorado