CMP-MSI: 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects
In conjunction with the
Saturday, January 9th, 2010
Bangalore, India
Scope:
Chip multiprocessors (CMPs) have emerged as the architecture of choice in both general purpose processors as
well as in embedded systems. Modern CMPs integrate several high-performance processing cores as well as
accelerators onto the same chip. A high performance interconnect and memory system is necessary to satisfy the
data supply needs of all the processing units, especially given the ever increasing speed gap between processors
and main memory systems. This year, emphasis will be given to the memory needs of on-board fixed function
units/accelerators and exploration of suitable memory and interconnect architectures.
This workshop aims to remain a premier forum for academia and industry to discuss and present ideas related to
architecture, design and evaluation of on-chip multiprocessor memory systems and interconnects.
Call for Papers:
Two kinds of papers are invited:
- Technical papers (at least 6 pages) for relatively mature ideas.
- Position papers (3 pages maximum) on directions for research and development.
Please submit an electronic copy of your paper (in PDF) in two column format with at least 10pt font. Please submit an abstract (less than 300 words) a week before the paper submission deadline. Paper submissions will be accepted through Nov 10th even if an abstract was not submitted early. Submission site . For questions regarding the submission site, please send email
to the Web Chair .
The selected papers will be made available online. However,
publication in CMP-MSI does not preclude later publication at regular
conferences or journals.
Topics of interest include:
- Novel memory and interconnect architectures for many-core CPUs and SoCs
- Memory system architecture for specialized multi-core chips for gaming, networking, media, financial and scientific applications
- Interconnect design and optimizations
- Policies for non-uniform cache access (NUCA) and shared/private caching
- 3D stacked cache hierarchies
- Improvements to cache hierarchy, power, reliability, security and complexity
- Coherence optimizations
- Impact of interconnect and memory on the performance and ease of parallel programming models/environments
- Support for software optimizations and/or enhanced functionality
(e.g., debugging, tracing, check pointing)
- Workload characteristics of SoCs with special emphasis on memory interfaces and memory access
- Communication protocols between cores, caches and accelerators
- Early reports on system prototypes
Important Dates
Abstract due (optional): Monday November 2, 2009
Paper Due: Monday November 9, 2009
Notification: Monday November 23, 2009
Final Paper Due: Monday December 14, 2009
Submission site
Organizers
Mani Azimi, Intel Labs
Rajeev Balasubramonian , University of Utah
Partha Kundu , Intel Labs
Web Chair
David Nellans , University of Utah
Program Committee
Dave Albonesi, Cornell
Mani Azimi, Intel Labs
Rajeev Balasubramonian, Univ. of Utah
Davide Bertozzi, Univ. of Ferrara
Mainak Chaudhuri, IIT Kanpur
Sangyeun Cho, Univ. of Pittsburgh
Natalie Enright Jerger, Univ. of Toronto
Yuho Jin, USC
Anshul Kumar, IIT Delhi
Partha Kundu, Intel Labs
Andreas Moshovos, Univ. of Toronto
Naveen Muralimanohar, HP Labs
Li-Shiuan Peh, MIT
Yiannakis Sazeides, Univ. of Cyprus
Andre Seznec, Irisa/INRIA
Li Shang, Univ. of Colorado
Previous Workshops
CMP-MSI 2009
CMP-MSI 2008
CMP-MSI 2007