Fall 2005: CS 7937 Architecture/Async Seminar

General Information:

• Venue: MEB 3105
• Time: Tuesdays, 2-3:30pm
• Instructors: Rajeev Balasubramonian and Al Davis
• Class mailing list: arch-rd-club@cs.utah.edu. Visit the mailman system to sign up or modify.

Class Schedule

• Tue 30th Aug: Organizational Meeting
• Tue 6th Sept: Karthik : "An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors" , N. Clark, J. Blome, M. Chu, S. Mahlke, S. Biles, K. Flautner, Proceedings of ISCA-32, June 2005.
• Tue 13th Sept: Naveen : "Mitigating Amdahl's Law Through EPI Throttling" , M. Annavaram, E. Grochowski, J. Shen, Proceedings of ISCA-32, June 2005.
• Tue 20th Sept: Dave : Practice talk for PAC2. "A Case for Increased Operating System Support in Chip Multi-Processors" , D. Nellans, R. Balasubramonian, E. Brunvand, 2nd IBM Watson Conference on Interaction between Architecture, Circuits, and Compilers, September 2005.
• Tue 27th Sept: Zhen : "A Distributed Control Path Architecture for VLIW Processors" , H. Zhong, K. Fan, S. Mahlke, M. Schlansker, Proceedings of PACT-14, September 2005.
• Tue 4th Oct: Nate: "Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache" , R. Ravindram, P. Nagarkar, G. Dasika, E. Marsman, R. Senger, S. Mahlke, R. Brown, Proceedings of CGO, March 2005.
• Tue 11th Oct: No Meeting :
• Tue 18th Oct: Niti : "Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance" , M. Rashid, E. Tan, M. Huang, D. Albonesi, Proceedings of PACT-14, September 2005.
• Tue 25th Oct: Rajeev : "Implementing Caches in a 3D Technology for High Performance Processors" , K. Puttaswamy, G. Loh, Proceedings of ICCD, October 2005.
  "On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions" , M. Haurylau, H. Chen, J. Zhang, G. Chen, N. Nelson, D. Albonesi, E. Friedman, P. Fauchet, 2nd International Group IV Photonics Conference, September 2005.
• Tue 1st Nov: Vamshi : "Limits to Performance Spread Tuning Using Adaptive Voltage and Body Biasing" , M. Meijer, F. Pessolano, J. deGyvez, Proceedings of ISCAS 2005.
  "Combined Dynamic Voltage Scaling and Adaptive Body Biasing for Lower Power Microprocessors under Dynamic Workloads" , S. Martin, K. Flautner, T. Mudge, D. Blaauw, Proceedings of ICCAD 2002.
• Tue 8th Nov: Liqun : "Shader Performance Analysis on a Modern GPU Architecture" , V. Moya, C. Gonzalez, J. Roca, A. Fernandez, R. Espasa, Proceedings of MICRO-38, December 2005.
• Tue 15th Nov: Abhishek : "Access Pattern-Based Memory and Connectivity Architecture Exploration" , P. Grun, N. Dutt, A. Nicolau, ACM Transactions on Embedded Computing Systems, Vol. 2, No. 1, February 2003.
• Tue 22nd Nov: No Meeting :
• Tue 29th Nov: Dan : "Niagara: A 32-Way Multithreaded SPARC Processor" , P. Kongetira, K. Aingaran, K. Olukotun, IEEE Micro, March-April, 2005. Slides
  Notes on the Cell processor
• Mon 5th Dec (11:45am-1pm, LCR): Tim Ameel : Tutorial on microscale heat transfer.