CS/EE 5830/6830
VLSI Architecture
Spring 2007

General Information

Important Information

Course Description

In general VLSI Archtitecture is a class that looks in depth at a particular application domain and how that domain interacts with VLSI implementation. This year we'll be looking at Arithmetic circuits and systems. We will look in detail at arithmetic subsystems and do projects based on studying and characterizing the behavior (speed, power, size, etc.) of various arithmetic subsystems for VLSI.

Grading

Grading will be based on participation. Note that grad students registered for 6830 will be expected to read and evaluate two additional papers so the grading scale is slightly different for 6830. Expected participation includes:

Notice that although this is a project-based class, much of the grade is based on writing about your results! Plan now to spend to spend some time preparing a nice final paper and report document!

For the final project, all team members will receive the same grade. However, there will be a chance at the end of the semester for all team members to confidentially evaluate the contribution made by their teammates to the project. If there is enough evidence that a team member did not contribute effectively to the project, I may reduce that team member's project score to account for this.

There will be some additional assignments for CS/EE6830 students involving reading, summarizing, and possibly presenting papers related to the subject of the course.

Crafting a Chip: A Practical Guide to the University of Utah CAD Flow

We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they aren't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve.

I'm in the process of rewriting all the tool tutorials and putting them in book form as a CAD tool lab manual. Draft chapters are complete, but will likely be updated during the semester. You are, of course, free to read the CAD tool documentation and learn more if you like. However, I encourage you to start with the Lab Manual because I know that using the tools in this way works. If you discover some new trick about using the tools, I'd love to hear about it!

The following draft book chapters are in PDF format:

q       Title page and table of contents

q       Chapter 1: Getting Started

q       Chapter 2: Cadence Design Framework

q       Chapter 3: Composer Schematic Capture

q       Chapter 4: Verilog Simulation

q       Chapter 5: Virtuoso Layout Editor

q       Chapter 6: Spectre Analog Simulation

q       Chapter 7: Cell Characterization

q       Chapter8: Verilog Synthesis

q       Chapter 9: Abstract Generation

q       Chapter 10: SOC Encounter Place and Route

q       Chapter 11: Chip Assembly

q       Chapter 12: Design Example: TinyMIPS

q       Appendix A: Tool Administration

q       Appendix B: Highlights of the Tools

q       Appendix C: Tool and Startup Scripts

q       Appendix D: MOSIS SCMOS Rev8 Design Rules

q       Appendix E: Technology and Cell Libraries

q       Bibliography and Index

q       A paper by Allen Tanner about the makemem memory generator

q       A tutorial demonstration of the makemem program generating a ROM and an SRAM

q       A tutorial on the Cadence-Synopsys Interface (CSI) which lets you netlist a schematic into structural verilog for input to Synopsys.

q       A tutorial from a couple years ago about timing options for simulation. It may not be exactly correct for out current version of the tools, but it's a good overview of simulation timing options (unit-gate-delay, unit-transistor-delay, SDF delay, analog sim, and mixed analog/digital sim).

q       Chapter one from Sutherland, Sproull, and Harris' book on Logical Effort is here in PDF. The website for the book is located here

q       A tutorial about power measurement using SpectreS can be found here in PDF

Assignments

Helpful Info

There's a lot of good info on the CS/EE 5710/6710 Digital VLSI class web site that you might want to look at.

Look in the Tool Information part of that web site for useful info about Verilog, for example. THere are some quick reference guides and tutorials that can give you good information about Verilog as a language.

Here's information about using VNC to run the tools remotely courtesy of Mike Lodder. Using VNC to display the cade desktop through the network on your home machine is much faster than direct X11 tunnelling of the Cadence tools to your desktop X server...

Slides

Lecture Plan

We'll basically follow the textbook in terms of subjects, although I will likely bring in additional material for some topics. Listed here is the general plan for the order in which we'll look at material, but I don't have a good feel for how long we will need to spend on each topic so I'm not going to try to put dates in the lecture plan. Interspersed with the arithmetic topics will be lectures on using the various CAD tools that you'll need for the assignments and for the projects.

Arithmetic Circuit Topics

CAD tools and circuit topics (interspersed with arithmetic topics!)