CS/EE 5710/6710 Syllabus
Digital VLSI Design
Fall 2007
General Information
- Instructor: Prof. Erik Brunvand
, 581-4345. Office is MEB 3142. Please use the teach-cs6710@cs mailing list to send email about the class.
- Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment
- TA: Toren Monson Please use the teach-cs6710@cs mailing list to send email to the TA.
- Office hours in the CADE lab - Mon 1:30-4:30, Wed 12:00-3:00, Thur 3:30-6:00.
- Class: T-Th, 12:25-1:45, WEB 1250
- Prerequisites: CS/EE3700 (Digital Design) or equivalent is required.
CS3810 (Computer Architecture) equivalent is extremely helpful.
This is a class in VLSI design not in digital system design, I'll assume that you know how to design and implement combinational and sequential circuits digital (i.e. finite state machines, data path circuits, and using FSM's to control datapaths). The project will be based on building a digital standard cell library and then using it to build a digital system so knowing some computer architecture will definitely help. You should be comfortable with computer CAD tools for hardware design. We'll be using tools from Cadence and Synopsys. You don't need to know these tools specifically, but I'll assume that you've used CAD tools of some sort. - Textbook: Principles of CMOS VLSI Design: A Systems Perspective (3nd Edition), By Neil Weste, David Harris, Published by Addison-Wesley, c2005, ISBN 0-321-14901-7. Note that there are some Errata (mistakes) that are listed here.
- There are two class mailing lists:
- cs6710@cs.utah.edu is a list of everyone in the class. I'll use this list to send important information to everyone in the class so you need to add yourself to that list! You can add yourself to this list and see archived messages at http://mailman.cs.utah.edu/mailman/listinfo/cs6710. You can also send email to this list, but be aware that it goes to *everyone* in the class, so be sure this is what you really want to do.
- teach-cs6710@cs.utah.edu Email sent to this list will go to both the professor and the TA. This is BY FAR the preferred method of asking questions! It lets all the teaching staff see and respond to the questions. Please use this email address unless you have very specific reasons for only sending email to one person.
Important Information
q College guidelines for adding, dropping, and other administrative issues can be found here.
q Cheating will not be tolerated! A discussion of this issue can be found here
q The
Course Description
This course introduces mask-level integrated circuit design for digital circuit design. Correct engineering design methodology is emphasized. Topics covered in lectures include:
q CMOS processes
q Mask layout methods and design rules
q Circuit characterization and performance estimation
q Standard cell design and use
q Custom data path circuit design
q Use of CAD tools for VLSI design
q Design for testability
q CMOS subsystem and system design.
This is a project-oriented course in which you will design a modest-sized CMOS integrated circuit. Except for the occasional tutorial session, no specific lab times are scheduled, and you can work at your convenience.
The homework assignments and the project will require the use of the workstations in the CADE lab (Cadence and Synopsys run only on Solaris and linux machines – not Windows). Students must have an account that will allow them to use the CADE machines, and some familiarity with UNIX and X-windows will be assumed.
Integrated circuit design is mastered only through experience. The homework, as well as lectures, will be closely tied to the term project, the design of a simple standard cell library and then the use of that library to design a project. The initial design of cells for the project will be done individually. You must complete the design of these cells on time. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own.
The final library and project will be done in teams. The project must be completed, and you must submit a final report in the format specified.
Within the constraints of available funding, eligible projects will be fabricated through the MOSIS service. If your project is fabricated, it must be tested; you can get credit for testing it in CS/EE 6770 or as an independent study project. You are encouraged to enter your design in the DAC (Design Automation Conference) Student Design Contest.
Tutorials on the CAD tools
We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they aren't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve.
I’m in the process of rewriting all the tool tutorials and putting them in book form as a CAD tool lab manual. Draft chapters will appear here as they are available. You are, of course, free to read the CAD tool documentation and learn more if you like. However, I encourage you to start with the tutorials because we know that using the tools in this way works. If you discover some new trick about using the tools, I’d love to hear about it!
The following draft book chapters are in PDF format…
q Title page and table of contents
q Chapter 2: Cadence Design Framework
q Chapter 3: Composer Schematic Capture
q Chapter 4: Verilog Simulation
q Chapter 5: Virtuoso Layout Editor
q Chapter 6: Spectre Analog Simulation
q Chapter 7: Cell Characterization
q Chapter 9: Abstract Generation
q Chapter 10: SOC Encounter Place and Route
q Chapter 12: Design Example: TinyMIPS
q Appendix A: Tool Administration
q Appendix B: Highlights of the Tools
q Appendix C: Tool and Startup Scripts
q Appendix D: MOSIS SCMOS Rev8 Design Rules
q Appendix E: Technology and Cell Libraries
q Bibliography and Index
q A paper by Allen Tanner about the makemem memory generator
q A tutorial demonstration of the makemem program generating a ROM and an SRAM
q The VGA mini-project from 2005 which has lots of details on how to get a VGA controller working. Check out the text message option for details on using the charROM to make characters on the screen. Note that some of the details from 2005 aren't relevant any more, like the stuff about Silicon Ensemble. We now use SOC. But,the specs on VGA are still good.
Assignments and Labs
The labs for this class are on a very tight schedule in order to complete the project by the end of the semester. Any slip in the schedule will cause lots of headaches later on! Students will need to be aware of the schedule and complete labs on time. There is generally no provision for late work.
The lab contents will be available here as soon as we have them ready...
At some point we're going to start electronic handin of much of the assignment (stay tuned for details). General instructions for the CADE handin process are located here. Instructions for each specific assignment will be either in the assignment or emailed to the class mailing list.
q Review assignment. In PDF. This assignment will be graded! It will just be graded pass/fail though. If you can answer all the questions easily then you probably have the right background for this course. If you can't, you will need to brush up on some of your digital logic background! Please take this seriously! If you have trouble with this exam, you will also have trouble with the project! Due Friday, August 31st .
q CAD1: in PDF - Cadence schematic capture and Verilog simulation. Reading: CAD Manual Chapters 1-4. Due Friday August 31st .
q CAD2: in PDF - Virtuoso layout, DRC, LVS, Analog simulation. Reading CAD manual Chapters 5-6. Due Monday September 10th.
q CAD3: in PDF - FF/Register design. Reading: Lab Manual Chapters 3-6, Book Chapter 1 (section 1.4). Also peek ahead at Chapter 7. Due Monday September 17th. Turn in CAD3 electronically with handin!
q CAD4: in PDF - DC simulation, transistor operation. Reading: CAD manual Chapter 6, Book Chapter 2. Due Monday September 24th. For CAD4, please print out the various circuits and output waveforms and turn in on paper, or convert everything to PDF and use handin. We won't need the Cadence libraries, just the printouts (schematics, waveforms, book problems, etc.)
q
CAD5: in PDF
- Initial 5-cell Library. Group Assignment! Reading: CAD manual Chapters
7-8. Due Friday October 5th.
For CAD5 use electronic handin for your cell library project directory
(Lib6710_xx) and data directory (LibData_xx) as described
in the lab handout.
q
CAD6: in PDF
- Seven more cells to make a 12-cell Library. Group Assignment! Reading:
CAD manual Chapters 7-9, and the paper Compact
yet High-Performance (CyHP) Library for Short Time-to-Market with New
Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a
case that a small (11 or 20 cells) library can perform almost as well as a 400
cell library when used with Synopsys design compiler and standard
benchmarks. Due Friday October
19th.
For CAD6 use electronic handin for your cell
library project directory (Lib6710_xx), and data directory (LibData_xx) as
described in the handout.
q
CAD7: in PDF
- A few more cells, and place and route of a controller
example. Reading: CAD manual Chapter 10. Due
Monday October 29th.
Handin instructions are in the assignment.
q
Proposal: in
PDF - Tell me about the project you plan to design. Due Monday November 5th.
You
can print this assignment and put it in the box by the School of Computing
office, or you can use electronic handin of a PDF file using the "Proposal"
assignment name.
q Midterm Exam - the exam, which isn't really at mid-term, will be on Tuesday November 20, 2007 during class. It will be closed notes and closed book. Here is a sample exam to give you some idea of the type of thing to expect, and the format of the exam.
q You can find the charROM character ROM in the /uusoc/facility/cad_common/local/Cadence/lib/charROM directory. This is a ROM produced by Allen Tanner that contains characters that you could use with a VGA controller. You can use the library manager to add this charROM library to the set of libraries that you can see. You can find a data sheet for the charROM here.
q
Final Report Specs: in
PDF - your group's final report documentation Due Wednesday December 12th at 5:00pm.
You
can print this assignment and put it in the box by the School of Computing
office, or you can use electronic handin of a PDF file using the "Report"
assignment name. There are three parts to the final report - see the document.
q Group Evlaution Form This is a form you should use to evaluate you and your group in terms of what everyone did. Every group member should fill out their own copy of the form and turn it in separately. This is a confidential evaluation where you can tell me how well you think the rest of your group did. Due on Friday of Finals Week.
q Class evalution form This is a form you can use to give me confidential feedback on how you think the class went this semester. Let me know what you liked and didn't like, what worked, and what could have worked better. You don't need to sign this form!
Lecture Slides
I'll put the slides up here as they become available.
q Slides for lecture 1: intro, CMOS transistors as switches. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 1, sections 1.1-1.4
q Slides from David Harris on transistor-level gate design. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 1, Section 1.4.
q Intro to Layout, Design Rules. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 1, section 1.5 (and Chapter 6)
q More Layout (NOR example), intro to Verilog testbenches. Available in PDF six to a page and in PDF two to a page, Reading: Verilog companion text, Verilog docuements linked from this class web site.
q More detailed intro to Verilog testbenches. Available in PDF six to a page and in PDF two to a page, Reading: Verilog companion text, Verilog docuements linked from this class web site.
q
Even more Layout (line of diffusion layout, Euler diagrams, stick diagrams). Available in PDF six to a page and in PDF two to a page, Reading: Chapter 5, section 5.3 in particular
q MOS Transistor Theory Available in PDF six to a page and in PDF two to a page, Reading: Chapter 2, 4.
q CMOS processing and fabrication. Available in PDF six to a page and in PDF two to a page, Reading: Chapter 3
q Logical Effort transistor sizing available in PDF six to a page and in PDF two to a page.
q Logical Effort slides from David Harris (the co-author of our textbook, and co-author of the Logical Effort book) available in PDF six to a page and in PDF two to a page.
q Verilog for Synthesis. available in PDF six to a page and in PDF two to a page.
q Lightening tour of Design Compiler and SOC Encounter. available in PDF six to a page and in PDF two to a page.
q Slides on datapath circuits. available in PDF six to a page and in PDF two to a page.
q Slides on displays and VGA controllers. available in PDF six to a page and in PDF two to a page.
q
Slides on memory circuits. available in PDF six to a page and in PDF two to a page.
q
Slides on pads, pad frames, and finishing up. available in PDF six to a page and in PDF two to a page.
q
Slides on chip assembly using the Cadence Chip Assembly Router (ccar). available in PDF six to a page and in PDF two
to a page.
Grading Policy Grading will be based on participation. Expected participation includes: o Homework: Written homework will take the form of problem sets, project proposals, and other written work. o Labs: Labs involve mask-layout design of cells that will be used in your semester project. We will use CAD tools from Cadence runing on Solaris and linux. o Mid-term Exam: There will be one exam given sometime in the middle of the semester. o Class Project: The class project is the design of a small digital standard cell library and the use of that library to design a moderate-sized project. Each team will implement the baseline cell library, and propose additional circuits to tailor their library to a specific application area. Graduate projects (6000-level) will be required to be "more interesting" than the undergraduate projects. Graduate students will also be required to read and review two papers relating to VLSI from journals or conferences in the area. More details about this as class progresses. Project grading will be divided into two areas of importance. The first of these is design quality, which means soundness of engineering design (appropriate design trade-offs) and ingenuity at all levels of the design activity. This will be evaluated with equal weight placed on: § complexity: the number of extras added to the baseline library, and the complexity of the project built with the library. § application/systems decisions: evaluates whether intelligent decisions were made in making the design fit the application. § implementation quality: evaluated in three areas: datapath, chip-floorplan, and circuit design. Datapath evaluation will look at pitch-matching, over-cell routing, density, power routes, etc. Floorplanning will evaluate chip planning and how well things fit together. Circuit design will evaluate the quality of the custom transistor design. § completion: will look at how far the project progressed. Mask level LVS/DRC results will be looked at as well as simulation results and whether the chip is ready of MOSIS fabrication. Note that ingenuity is usually seen in simplicity, rather than added complexity. Credit will be given for doing things the right way, rather than the easy way. The second area is documentation. The final report should include an application-based specification and a clear description of your resulting chip implementation. The report must follow the format for an entry in the DAC Student Design Contest. An example will be given in class. No credit will be given for late reports. Each member of a project team will typically receive the same grade for the final project and for the project cell designs. If a particular group member is not contributing substantially to the project effort, his or her project grade and cell design grades will all be reduced by an appropriate percentage. Each group member will be given a peer contribution form to assess team member's efforts on each project-related assignment. These forms will be collected in the middle and at the end of the semester. Percentages for grades are as follows: § Labs (cell designs) & Homework: 40% § Design Review: 5% § Mid-term Exam: 15% § Project (design and report) 40% Helpful Information General Information q
Here's a link to a page with
lots of VGA timing info. Note that this is "official timing"
information, and most VGA displays are quite forgiving if you are
consistent with your own timing. q
This page from the
XESS company has some examples of VGA controllers targetted at
their Xilinx-based boards. So, memory details would have to be
finessed for custom chips, but the basics might be
interesting. The appnote for the simple controller for
the ancient XS-40 board is a good basic design, although it's in
VHDL in the appnote... q
Here's a link to a site with information about
interfacing to a PS/2 keyboard and mouse. It describes the timing interface
and the communication protocol that keyboards and mice use to send data through
that link. Note that PS/2 keyboards, for example, don't send ascii. They send
"make codes" and "break codes" on key press and key release that encode which
physical key has been pressed. You need to map those keys to the letters using
those codes if you want ascii. q Chapter one from Sutherland, Sproull, and Harris' book on Logic Effort is here in PDF. The website for the book is located here q A document by Eric Marsman from q A guide to basic electronics including MOS transistors: Appendix B from Contemporary Logic Design by Randy Katz. You don't need to know the sections on bipolar or diode logic. The MOS section is the most important. q Errata (mistakes) in the class textbook, q The SCN3M_SUBM SCMOS design rules from MOSIS, translated to microns, in PDF format, and in Word format. q The official SCMOS Rev8 design rules at MOSIS q A link to Reid Harrison's CS/EE 5720/6720 Analog VLSI class. They are also using the NCSU CDK and the SCMOS rules so you can find more information here including tutorials on analog simulation of designs built with the NCSU CDK, and a layout tutorial. q Information on Chip Fabrication at USC Information Sciences Institute (ISI): MOSIS (MOS Implementation Service) home page q LaTeX style files for producing IEEE-formatted two-column papers: A .cls style file with formatting information, a .bst bibliography style file, and a sample .tex file that demonstrates how it all should be used. q A Microsoft Word example file that shows how to get an IEEE format in MS Word. q A data sheet on the HM6264 8kX8 SRAM from the DSL lab kits. This is a good example of a generic SRAM that shows read and write protocols. q Documentation from Tanner Research about their digital pads in PDF. We'll be using these pads for our chip designs. q A page from Americn Microsemiconductor that has lots of tutorials on various semiconductor topics. q Here's a paper that I wrote a few years ago that describes a simple stack based architecture similar to the transputer that might make a great project. Even if you don't use this exact architecture, stack-based machine make nice simple processor architectures for those wanting to do a processor project. You definitely don't have to do this as a self-timed processor! It's a perfectly good synchronous stack machine too. q Here are a couple papers from the Journal of Solid State Circuits about latches and flip flops. These are just a couple examples, there are lots of papers about this! These papers analyze different latch and flip flop circuits for speed and power performance. o Comparative Analysis of Master Slave Latches and Flip-Flops for High-Performance and Low-Power Systems by Vladimir Stojanovic and Vojin G. Oklobdzija o New single-Clock CMOS LAtches and Flipflops with Improved Speed and Power Savings by Jiren Yuan and Christer Svensson q Compact yet High-Performance (CyHP) Library for Short Time-to-Market with New Technologies by Nguyen Minh Duc and Takayasu Sakurai. This paper makes a case that a small (11 or 20 cells) library can perform almost as well as a 400 cell library when used with Synopsys design compiler and standard benchmarks. Tool Information (Cadence, Synopsys, Verilog, etc. ) q Single-page reference sheet on Verilog syntax. This is the language used by the Verilog-XL simulator in Cadence. Use this as the equivalent of the ViewSim command language in Powerview. PDF format q A Verilog Quick Reference guide (in Postscript) q Another Verilog guide, this one is a lab from another class, but it talks about simulating Verilog code using the Verilog-XL simulator. q
Yet another Verilog guide. This
one is an introduction to Verilog from Daniel C. Hyde at q
A set of documents from Synopsys that describe good Verilog
coding style for synthesis. They are all in PDF. These files are linked
together if you're using the Acroread plugin to netscape or IE. Open the Table
of Contents and you should be able click on the chapters in that file to open
up the chapters. Note that these files are only accessable to CS/EE
5710/6710 students
q
A reference manual from Synopsys describing the Verilog synthesis
engine. Note that these files are only accessable to CS/EE
5710/6710 students q Here's a directory that has all the help files for the Module Compiler Express cells Project Information q Some project ideas in Word, in HTML and in PDF. q A description of the Instruction Set Architecture (ISA) of an example class processor. This is the description from the q Some slides from EECS 427 at q A CR16 lecture from CS/EE 3710 last year: Six per page, PDF This isn't quite exactly the same as the q PDF version of CR16A Programmer's Reference Manual. This is the manual that describes in detail the operation of the real CR16, and Appendix A has the details of the "real encoding" should you want to use that for your project. Note that this document is 94 pages long... q Home page at National for a bunch of other CR16 documents. Note that we are more interested in the CR16A than in the CR16B, although they are very similar. q Information about the DAC student VLSI Design contest Reference Material q David Hodges, Analysis and Design of Digital Integrated Circuits (3rd ed), McGraw Hill, 2004. q Wayne Wolf, Modern VLSI Design (3rd ed), Prentice Hall, 2002. q Jan M. Rabaey, Digital Integrated Circuits (2nd ed), Prentice Hall, 2003. q Glasser and Doberpuhl, The Design and Analysis of VLSI Circuits, (most detailed circuit treatment), Addison-Wesley, 1985. q Michael J. S. Smith, Application-Specific Integrated Circuits, (new, comprehensive, advanced level) Addison-Wesley, 1997. q Hodges and q Hennessy and Patterson, Computer Organization & Design - The Hardware/Software Interface, (3810 text) Morgan Kaufmann, 1994. q IEEE Journal of Solid-State Circuits I q EEE Trans. on Computer-Aided Design of Integrated Circuits and Systems q IEEE International Solid-State Circuits Conference, 1954 - q Advanced Research in VLSI, 1980- q IEEE Custom Integrated Circuits Conference, 1979 - q EE Times, Electronics, Computer Design, EDN...
Last year the VGA controller was a CAD assignment for everyone. The assignment and specs for the assigned VGA controller from last year can be found here. The specs and description may help you getting your own VGA controller to work. Note that the tutorials pointed to by last year's assignment aren't valid. You should be using our CAD Manual flow.