CS / ECE 3710: Computer Design: Fall 2004
(AMD 486 (left) and Power-5 16-way multiprocessor with 2 processors per
chip and 8 chips per module (right); Click for larger images)
General Information:
This class will be
taught as a dialog between students and myself / TA. The dialog shall
occur either in class or thru emails ( t_e_a_c_h-c s 3710 at cs
dot_utah_dot_edu).
We will respond by creating directories in the FAQ link below.
Discussions will be in separate sub-directories (folders) such as
"lec1" , "lec2" , etc. Kindly search thru
the FAQs before you ask us questions. Of course we will most
likely refer you to the FAQs should you
ask redundant questions. A class of this magnitude of "information
complexity" is best taught by your
asking me / TA questions and us answering you -- not by us flooding you
with info, because you will find
most info we might give not matching what you are seeking right at a
given moment.
- Office Hours:
- Ganesh office hours: 2-3pm Tue, 5-6pm Thu, 3428 MEB
- DSL lab hours (also TA office hrs): 10-11am Mon,
4.00-6.00pm Wed - 3133 MEB (ID card access)
Lectures: 3.40-5.00pm, sometimes in EMCB 104, mostly in 3133 MEB
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Lecture-specific information:
- Warmup Exercise (due by 9/10/04)
A circuit called 'pet' was
the
final project of CS 3700 during Spring'04. I've re-designed 'pet' as
follows:
- It is now in VHDL
- It uses an SDRAM present on the XSA board in lieu of a VHDL array
that was originally employed
This new design is being
offered as a warm-up exercise for the class. It is also a good
candidate
to convert
to the design language "Confluence." The details are in
the
links below.
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For instructors:
