CS/EE 3710 - Computer Design
Fall 2002

General Information

Lectures

This is a lab class. Although there are lectures scheduled on Tuesday and Thursday from 3:40pm - 5:00pm, the main point of the class is the project. The lectures will present material related to the project, and there will be TA hours held in the digital systems lab (MEB 3133) both so that you can get help from the TA, and also to check off project milestones.

Prerequisites

CS3700 (digital design) and CS3810 (computer architecture) or equivalant classes

College Guidelines

College guidelines for adding, dropping, and other administrative issues can be found here.

Web Page

Information about the course, copies of the handouts, and other information will be available on the class web page at http://www.cs.utah.edu/classes/cs3710 (which you probably already know, since you're looking at it!)

Course Objectives

This is a laboratory class in which groups of students (groups can be of size 3 or 4) design, build, and test a simple computer. The idea is to use the digital design skills from 3700, and the computer architecture knowledge from 3810, and put it all together in a semester-long project. There is no text for this class, and there will be no midterm exams, although there will be a final exam. There will be a few intro labs, but the main class work is a laboratory project that will be divided up into parts that are due over the course of the quarter to help you budget your time. In addition to demonstrating your working hardware, a final written report will be required. This report will document your design, and will be due on the last day of class, Thursday Dec 5th.

The implementation technology for this version of CS3710 will be different than in CS/EE 3700. Instead of the lab kit boards, we'll be mostly using boards from Xess that feature a Xilinx SpartanII FPGA, 16Mbytes of SDRAM, and some other goodies that we'll go over in class.

All projects will be designed and simulated using the Viewlogic tools. You'll also have assess to the Xilinx ISE design tools which you can use if you choose, but the instructor and TA won't be able to help you as much with these tools.

We will also be able to use VHDL for control state machine in parts of your design. We will use the fpga_compilerII VHDL synthesis tool from Synopsys in conjunction with the Fusion simulator for this.

Grading

Approximate weights are as follows:

Lab Partners

You must choose a lab partner or partners as soon as possible and let Erik and the TA know who the groups are. Groups should be 4-5 persons.

Design Tools

I'd like all groups to use Powerview for designing their projects. We will have to use Xilinx ISE for the final stage of mapping to the FPGA, but I think it will cause far fewer problems if we all use the same tool for drawing schematics and simulating both circuits and VHDL.

Use the class bsheet, or copy it and modify it for your own team. Make the text in the schematics big enough to read, and take the time to make your schematics look nice (straighten wire jogs, line up components, don't put too much on one sheet, etc etc). I'm sure you'll remember this from CS/EE 3700!

You should also remember that espresso and misII are available that you used in CS/EE3700.

The version of Fusion that we'll be using is a newer version than we used in CS/EE 3700. This is specifically to support the Xilinx SpartanII chip on the Xess board. The interface looks different (mostly it's in a different color), but it's really just the same interface you used last semester. The only thing that's changed a bit is the VHDL library setup procedure. The tutorial will go over that.

Handouts and Assignments

Tool Information

Lecture Slides

Helpful Links

Xess Board and Xilinx FPGA Info I/O datasheets and information National Semiconductor CR16 Processor Info