Table of Contents

• 1  Introduction
• 2  References
• 3  Administrative Matters
• 4  Calendar
• 5  ADA Statement
• 6  Groups
• 7  Meeting Schedules
• 8  Meeting Agenda

1  Introduction

• General information such as Project Group Name, Group Number (to be assigned by us), and Member Names
• A Mailto link by clicking which we can email all project group members in one email
• A list of updates specific to each week; for example
  • A clickable URL which says ``Updates for Aug 29'' and below that similar update links for each week.
• Other links that describe the project.

1. 10 points - A take-home final exam given during the exam week, and solved individually by each student. This will test your basic understanding of digital design, including state machine design and the ability to approach the design of a medium-sized digital system.
   
   
2. 45 points - Final project demo + project report. The project demo sessions will be on 12/5/06 and 12/7/06. The project report consists of last minute updates to the project webpage (see below) and a good summary statement of the highlights of the project (also added to the webpage). No printed project report needs to be turned in.
   
   
3. 45 points - Weekly progress updates per group. Since there will be roughly 12 meetings, each week's work is worth roughly 4 points (or each member's work per week is worth roughly one point).
   • During one week, the odd-numbered groups will meet me between 3.00pm and 5.00pm (roughly; subject to adjustments). Each group will receive about 30 minutes. The same week, the even-numbered groups will meet one of the TAs (the TAs will take turns, as you can see below).
   • To avoid all confusion, using one-letter abbreviations for our first names, here is the meeting order
     • for odd-numbered groups: GAGNGAGN...
     • for even-numbered groups: AGNGAGNG...
   • So, the above means that I'll get to see groups 1,3,5,7 one week, and 2,4,6,8 the next week.
   • Aaron will meet groups 2,4,6,8 during one week and then 1,3,5,7 the next week. Then Neal will meet 2,4,6,8 and then 1,3,5,7.
   • For meeting me (Ganesh), come to my office 3428 MEB. For meeting the TA, just stay in the DSL, and the TA in-charge will come to your table, and spend as much time as they think they need (30 mins or less).
   • The default order of arrival is by your group number. So when odd groups are involved, group 1 arrives at 3pm, group 3 at 3.30pm, and so on. If this is a problem, negotiate all switches between the groups and just show up (the exact order does not matter for me)
   • The instructor or TA meeting a group is responsible for assessing that group's progress over the week prior to the meeting (by studying the webpage and talking to the groups). We will promptly post the scores (within a week).
   • The purpose of these meetings: I would say that the purpose of the meetings is to prevent tardiness from setting in, and mainly to help you!
   I am allowing groups the option to call off meetings, and instead provide extensive updates through the webpages. This way, for routine updates, we don't have to be all dragged in. However, for required checkoffs, I am requiring that the TAs or I witness the checkoffs. The checkoffs can be witnessed during 1-1 meetings (need not happen in the DSL if the students have their laptops and the checkoffs don't need any additional DSL hardware).

• your free time slots, and
• preferred email addresses.

• Forming project groups for those with no group yet. Project group formations will occur in consultation with the concerned students. The idea is to form groups among those who have largely overlapping free time slots.
• The TAs will also try their best to align their office hours to match your free time slots.
• Please use the Email Interface cs3710-join@cs.utah.edu to join the class mailing list (just send an email with an empty subject + body). Please launch this email from your preferred email address.

2  References

3  Administrative Matters

• All labs will be held in the Digital Systems Laboratory (DSL) in room 3133 MEB. We are working on making your ID-card based 24/7 access possible.
  
  
• The only DSL staff person is Travis Stroud. Mr. Stroud's office hours are 11am to 5pm, except on Tuesdays he will stay only till 4.30pm. He will, to the best of his ability, address problems pertaining to chips, computers, etc. He sits in the same general area as the DSL lab (MEB 3133). (I'll check these hours once again.)
  
  
• Instructor Office Hours:
  • During our 1-1 meetings, which will be on Tuesdays 3:30 to 5:00pm in my office 3428 MEB.
  • Other meetings can be scheduled through email. I won't be available for the most part on Wednesdays and Fridays.
  
  
  
• Email Interface to join class mailing list (empty subject + body): cs3710-join@cs.utah.edu
  
  
• Class Mailing List Info: http://mailman.cs.utah.edu/mailman/listinfo/cs3710
  
  
• Class-related Email: teach-cs3710@cs.utah.edu

4  Calendar

        August              September             October               November              December
 Su Mo Tu We Th Fr Sa  Su Mo Tu We Th Fr Sa   Su Mo Tu We Th Fr Sa  Su Mo Tu We Th Fr Sa  Su Mo Tu We Th Fr Sa
                                       1  2    1  2  3  4 FB  6  7            1  2  3  4                  1  2
                        3  4  5  6  7  8  9    8  9 10 11 12 13 14   5  6  7  8  9 10 11   3  4  5  6 LD
                       10 11 12 13 14 15 16   15 16 17 18 19 20 21  12 13 14 15 16 17 18
             24 25 26  17 18 19 20 21 22 23   22 23 24 25 26 27 28  19 20 21 22 TG 24 25
 27 28 29 30 31        24 25 26 27 28 29 30   29 30 31              26 27 28 29 30

  

FB = Fall Break
LD = Last Day of classes

5  ADA Statement

6  Groups

7  Meeting Schedules

Group 1 meets Ganesh

3:40 to 4:00 PM on: Sep 5, Sep 19, Oct 3, Oct 17, Oct 31, Nov 14, Nov 28

Group 1 meets Aaron

3:40 to 4:00 PM on: Sep 12, Oct 10, Nov 7, Nov 28

Group 1 meets Neal

3:40 to 4:00 PM on: Sep 26, Oct 24, Nov 21

Group 2 meets Ganesh

3:40 to 4:00 PM on: Sep 12, Sep 26, Oct 10, Oct 24, Nov 7, Nov 21, Dec 5

Group 2 meets Aaron

3:40 to 4:00 PM on: Sep 5, Oct 3, Oct 31

Group 2 meets Neal

3:40 to 4:00 PM on: Sep 19, Oct 17, Nov 14, Nov 28

Group 3 meets Ganesh

4:00 to 4:20 PM on: Sep 5, Sep 19, Oct 3, Oct 17, Oct 31, Nov 14, Nov 28

Group 3 meets Aaron

4:00 to 4:20 PM on: Sep 12, Oct 10, Nov 7, Nov 28

Group 3 meets Neal

4:00 to 4:20 PM on: Sep 26, Oct 24, Nov 21

Group 4 meets Ganesh

4:00 to 4:20 PM on: Sep 12, Sep 26, Oct 10, Oct 24, Nov 7, Nov 21, Dec 5

Group 4 meets Aaron

4:00 to 4:20 PM on: Sep 5, Oct 3, Oct 31

Group 4 meets Neal

4:00 to 4:20 PM on: Sep 19, Oct 17, Nov 14, Nov 28

Group 5 meets Ganesh

4:20 to 4:40 PM on: Sep 5, Sep 19, Oct 3, Oct 17, Oct 31, Nov 14, Nov 28

Group 5 meets Aaron

4:20 to 4:40 PM on: Sep 12, Oct 10, Nov 7, Nov 28

Group 5 meets Neal

4:20 to 4:40 PM on: Sep 26, Oct 24, Nov 21

Group 6 meets Ganesh

4:20 to 4:40 PM on: Sep 12, Sep 26, Oct 10, Oct 24, Nov 7, Nov 21, Dec 5

Group 6 meets Aaron

4:20 to 4:40 PM on: Sep 5, Oct 3, Oct 31

Group 6 meets Neal

4:20 to 4:40 PM on: Sep 19, Oct 17, Nov 14, Nov 28

Group 7 meets Ganesh

4:40 to 5:00 PM on: Sep 5, Sep 19, Oct 3, Oct 17, Oct 31, Nov 14, Nov 28

Group 7 meets Aaron

4:40 to 5:00 PM on: Sep 12, Oct 10, Nov 7, Nov 28

Group 7 meets Neal

4:40 to 5:00 PM on: Sep 26, Oct 24, Nov 21

Group 8 meets Ganesh

4:40 to 5:00 PM on: Sep 12, Sep 26, Oct 10, Oct 24, Nov 7, Nov 21, Dec 5

Group 8 meets Aaron

4:40 to 5:00 PM on: Sep 5, Oct 3, Oct 31

Group 8 meets Neal

4:40 to 5:00 PM on: Sep 19, Oct 17, Nov 14, Nov 28

8  Meeting Agenda

Sep 5

1. Your webpages must be ready. I should be able to login and see the public and private sections.
2. Evidence of the self-assessment circuit having been finished must be present.
   
   One submission is sufficient for the whole group. However, I may ask any group member - picked at random - to explain the solution to me. I may also ask that member to explain how the finite-state machine works.

Sep 12

1. You will be asked to show evidence on the webpage that you have played with the pipelined SDRAM controller and the mock CPU connected to it, and that
   1. You understand how the mock CPU works
   2. You have studied roughly how the rest of the system works
   3. You have changed the mock CPU to read and write different numbers and are still able to confirm its logic
   
   
   
2. Given three distinct integers situated at locations EFFD, EFFE, and EFFF, you are asked to write an assembly program that starts from location F000 (ORG is F000) such that
   1. The program compares these three integers and finds the maximum
   2. If the largest number is situated at EFFD, it must write into location EFFC the value EFFD
   3. If the largest number is situated at EFFE, it must write into location EFFC the value EFFE
   4. If the largest number is situated at EFFF, it must write into location EFFC the value EFFF
   We will be asking you to discuss the logic of this program and the flag values at various places in the program. Those groups who give nice crisp answers within the allotted time will be rewarded with extra points. Practice your answer to me beforehand, if you wish (highly recommended). Your assembly code and your solution must be present on the webpage by the time you come to meet us.

Sep 19

1. The group members must show me how they are proceeding with the construction of the assembler and the simulator. I will check your understanding at least as far as the thin-slice instructions are concerned. All the documentation must be there on the webpage also.
   
   
2. We will have given you a dual-port unit with VGA and mock CPU. You must show evidence that you have used this design, and show the extent to which your circuit works.
   
   
3. You must present evidence that you can successfully use the Block RAM memory. I will be assigning a simple design (Fibonacci circuit) that you must show working (evidence on webpage).

Sep 21

I allowed everyone to checkoff the `fib' circuit and the `largest' circuit by the midnight of Sep 21st.

Sep 26

1. The group members must show detailed hardware flow-charts for the thin-slice hardware and control logic. This means the following (I have also indicated the readings):
   1. Read the excerpts from Tredennick's book handed out in class (the handout that talks about hardware flowcharts). This was also covered in a recent lecture (go find out which).
   2. Additional resources are provided in two textbooks kept in the lab. One book is by Brown and Vranesic - the book used in 3700. The other book is on microprocessor design in VHDL. You may find it useful.
   3. Also look at the last page of
      http://www.cs.utah.edu/classes/cs3710/handouts/3:9-7/ISA.pdf
   4. Based on these readings, you must draw one datapath that supports all the thin-slice instructions.
      
      
   5. Then you must show hardware flow-chart sequences (sequences of boxes) for each thin-slice instruction. Each state (rectangle) of these HW flow-charts mentions which mux is set in which direction, which latch is enabled, etc.
      
      
   6. On Tuesday, we will ask each group to step through the hardware flow-charts and ask them to explain how each instruction works.

Oct 3

1. Project options have been listed on the class webpage at
   
   http://www.cs.utah.edu/classes/cs3710/handouts/6:9-28/project-selections.html
   
   By the meeting time of this date, you must put on your webpage a 1-page description of the project you have chosen.
   
   
2. You must walk us through your thin-slice schematic and the associated VHDL files.

Oct 10

The thin-slice hardware must be able to simulate using the block RAM. You must present the simulation waveforms, schematics, and explain during our meeting how it all works.

This is a major milestone, carrying a lot of checkoff points.

Note that this milestone requires the thin-slice to work completely under simulation.

Oct 17

There must be evidence on the webpage that your thin-slice hardware is working 100%, at least using the block-RAM as the main memory. (Extra points for those who are able to make use of the SDRAM as the main memory.)

Also the assembler and simulator must be completely working for the thin-slice.

This is a major milestone, carrying a lot of checkoff points.

Note that this milestone requires the thin-slice hardware to work completely. Display the internal state of selected registers and flags using either the LED or the VGA interface.

We will be cancelling all lectures after Oct 24th.

Oct 24

Adequate progress towards the full design

Oct 31

Old version: Adequate progress towards the full design

New version: The hardware must be able to work with the SDRAM and VGA. This is also a major milestone.

I'm sure you wanted this to happen anyhow. This deadline is being posted so that you achieve this milestone sooner rather than later... as it will help you tons:

• helps you download / upload programs far more easily
• helps you debug your assembler thoroughly

Ideally the CPU must have advanced a bit more in terms of instructions with respect to the thin-slice (e.g. add a branch).

Requirements for checkoff: Checkoff your CPU hardware with the SDRAM and VGA working in some capacity. The CPU must be able to run a program that modifies the image being displayed by the VGA.

Nov 7

Adequate progress towards the full design

Nov 14

:

• Show the full baseline working in hardware with SDRAM acting as the program + data memory. Also the VGA must be demonstrated in conjunction with the real hardware.
• Show some assembly programs working fully. Explain what they do.
• Show the assembler / simulator (for those groups that never got that done).
• Explain your progress towards your final projects.

For those groups facing HW issues (things not working), they are required to find out exactly what works and exactly what does not, and lead us thru their design and the working/non-working parts with great patience. Then we might be able to help you get the designs to work. Without such fault isolation and ability to explain things to us, we can't help you. You are welcome to do this all well before Nov 14th. The TAs have been ever-available and have lots of experience to put to use. You however have to give them 'bite-sized' problems to debug for you (could be big bites, but still bite-sized).

Nov 21

Everyone must show evidence on their webpage that their CPUs are working along with the VGA controller on at least 6 assembly programs. These programs must be assembled using their own assembler. Their simulator must also be shown to be working on this date (evidence on webpage).

Nov 28

Each group must be able to argue, supported by evidence on webpage, that their CPUs are truly done, and that all that remains is to update the webpages.

Dec 5

Project Demos during extended lab time (3-5). Web pages must be fully updated.

Dec 7

Project Demos during extended lab time (3-5). Only last-minute items to close-off should remain.

This document was translated from L^AT_EX by H^EV^EA.