CS/EE 3700 - Digital System Design
Spring 2008

Tuesday-Thursday, 12:25-1:45, WEB 101
Prof. Erik Brunvand


Final Exam Schedule
Wednesday, April 30, 10:30am-12:30pm, in our regular classroom

"If you've ever opened up your computer to get all the pizza crumbs out, you probably noticed that there's nothing in there but a shiny green board covered with silver lines and lots of little black doodads. This class will attempt to teach you what those doodads are, how they work, and why it costs so much to fix when you spill stuff all over them."
- Bill Richardson, Former 3700 TA

A more formal definition of this class might be:

The purpose of CS 3700 is to introduce you to the fundamental concepts of digital system theory and design. This includes techniques for defining and minimizing logic functions, design of combinational and sequential logic circuits, state diagrams, Mealy and Moore finite state machine models, design with MSI and LSI parts, design with Field Programmable Gate Arrays (FPGAs), and system controller design. By the end of the course you should be able to understand digital problem descriptions, design and optimize a solution, and build, test, and debug the resulting circuit.

Teaching staff

The instructor is Dr. Erik Brunvand.
Phone: 581-4345. Office: MEB 3142. Please use the teach-cs700@cs mailing list to send email about the class.
Office Hours: Tuesday and Thursday after class, when my office door is open, or by appointment

Teaching assistants are Toren Monson, Ben Meakin, and Tilottama BoseMaiti

Prerequisites

CS 1410 (Intro to CS) or 2000 (Intro to Programming), and PHYCS 2220: Physics for Scien. & Engineering II.

College Administrative Guidelines

The College of Engineering Spring 2008 guidelines are here in PDF.

Textbook

Fundamentals of Digital Logic with Verilog Design, 2nd edition, by Stephen Brown and Zvonko Vranesic, c2008. Available at the University Bookstore and at various places on the web.

CAD Software

We'll be using the free WebPACK software from Xilinx (v9.2i) for the labs. We'll use this software for schematics, circuit and Verilog simulation, Verilog synthesis, and mapping circuits to the Xilinx FPGAs. You can download a free copy to your own PC at this Xilinx web site. You'll have to register, but it doesn't cost anything. This software will also be loaded on the lab PCs.

Class Mailing Lists

There are two important class mailing lists:

Meeting times

Office hours

Dr. Brunvand's hours are after class, whenever his door is open, and by appointment in his office (3142 MEB).

The TAs hold their office hours in the DSL. The times are:

Grading policies

THERE IS NO PROVISION FOR TURNING IN LATE LABS OR ASSIGNMENTS

Grading will be based on the following:

Final point totals will be scaled so that the best student in the class has 100%. All students will be scaled by the that amount. Grade ranges will be: Cheating will not be tolerated! A discussion of this issue can be found here

Assignments

Hand in hard-copy paper assignments in the box outside the School of Computing front office (MEB 3190). Make SURE to put your name and your lab section clearly on the front of the assignment. Partial credit is possible, but only if we can understand what you did, and how you reached that conclusion.

Lecture Plan

Here's a link to an initial lecture schedule. Things will almost certainly drift a little, but here's my plan at least. Please make SURE that you read the appropriate sections in the book BEFORE the lecture!

Handouts and Other Useful Information

ADA Statement

ADA Statement: The University of Utah ECE Department and School of Computing seek to provide equal access to its programs, services and activities for people with disabilities. If you will need accommodations in this class, reasonable prior notice needs to be given to the instructor and to the Center for Disability Services, 162 Olpin Union Bldg, 581-5020 (V/TDD) to make arrangements for accommodations. This information is available in alternative format with prior notification.