University of Utah
Department of Computer Science
Avalanche Scalable Parallel Processor Project
- Principal Investigator:
Al Davis:
Chief Architect.
- Co-Principal Investigators:
-
Erik Brunvand:
VLSI Design.
-
Mark Swanson:
Widget Message Passing Architecture and Protocol Design.
- Faculty Associates:
-
John Carter:
Widget DSM and Cache Design.
(see also the
Flux OS Project).
-
Ganesh Gopalakrishnan:
Protocol Verification.
(see also the
UV Project pages).
- Staff Members:
-
Ravi Kuramkote:
Cache and Distributed Shared Memory Protocol Design.
-
Marshall Soares:
VLSI Tools and Layout.
-
Leigh Stoller:
Message Passing Protocol and Simulation Tools.
-
Terry T Tateyama:
Widget Message Passing/Network Interface Hardware Design.
- Students:
-
Qi (Clare) Gao:
Networking Software.
-
Ravi Mohan Hosabettu:
Formal Verification.
-
Ketil Julsgaard:
VLSI Design.
-
Chen Chi Kuo:
Widget DSM/Network Interface Design.
-
Ratan Nalumasu:
Protocol Verification.
-
Mike Parker:
Hardware Design ("Cache Heat").
-
Lambert Schaelicke:
Hardware Design.
-
Lixin Zhang
Cache Optimizations.
- Undergrads:
-
Sam Larsen.
-
Mark William Stephenson.
This work was sponsored by
the Space and Naval Warfare Systems Command (SPAWAR) and
Advanced Research Projects Agency (ARPA),
Communication and Memory Architectures for
Scalable Parallel Computing,
ARPA order #B990 under SPAWAR contract #N00039-95-C-0018.
Feedback to <avalanche@jensen.cs.utah.edu>.
Last modified around February 6, 1998.