The goal of the Avalanche (Communication Memory Architectures) project is to enable the construction of usable and truly scalable parallel computing platforms that are not exorbitantly expensive yet still capable of achieving peta-op performance levels. In order to achieve reasonable cost it will be necessary to adopt an approach that takes advantage of the significant performance advantages and momentum already provided by commercial microprocessor and interconnect fabric development efforts. Low communication latency is the key to achieving performance scalability for both common parallel computation models, namely message passing and distributed shared memory. Unfortunately commercial high performance microprocessors and their memory systems are not well integrated with their I/O subsystems in terms of support for parallel processing. I/O subsystems have traditionally been designed for generality rather than performance but for parallel systems this is a defect. The problem is exacerbated by the fact that DRAM performance improves only by a factor of 3 every 10 years while processor performance doubles every 18 months. This widening memory gap has caused uniprocessor architects to deepen the memory hierarchy in order to balance cost and performance requirements.
However for parallel processing environments where communication is a frequent event this architectural style is problematic. The deep hierarchy causes a significant increase in the cache miss penalty to main memory. Placing incoming communication data in the top level of the hierarchy risks the conflict displacement of active data which reduces performance due to the degradation of memory latency induced by increased conflict miss rates. Placing inbound communication data in main memory artificially increases the effective communication latency since before it can be used the data must percolate up to the top level cache and thereby incur the expensive compulsory miss costs. increased memory latency penalty further restricts scalability.
The Avalanche project is developing a memory architecture that tightly integrates the processor, the entire memory hierarchy and the interconnect fabric to minimize the communication latency for both message passing and distributed shared memory applications.
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