With the change to the PA-8000 processor, we are no longer blocked waiting for HP to transfer its PA-7100 design database and tools. While a new learning curve for the 8000 series has begun, the tools and library choices may now be made independent of the choices HP made some years ago. Further we no longer need to count on old version of tools compatible with the old 7100 database. We are using more acceptable VHDL code rather than the Verilog and HP PLA languages, making our results more significant to industry and the research community.
The first integrated circuit is being specified. We are investigating a number of content-addressable memory (CAM) designs. The CAM used as tags in a cache is always in the critical path, whether or not there is a cache hit. It is therefore critical to optimize this portion of the cache controller in Avalanche. Also, we are including circuits to investigate process speed expectations.
Hspice has been benchmarked on our new HP workstation platforms. The combination of larger memory and a faster processor has improved performance by a factor of four. A mixed-signal CMOS integrated circuit was used to evaluate the HP system performance. The circuit is a sigma-delta modulator already built for another project. The modulator includes A/D, switched-capacitor sampling, and digital filtering. This combination requires frequencies two orders magnitude different to be concurrently applied to the part. Thus, simulation times have been extremely long in this research. Simulations which were taking on the order of six hours to complete, complete in about ninety minutes on the HP system. Further, circuits larger than we have ever been able to simulate (memory limitations) have been successfully simulated. The key test circuit was a seventeen thousand transistor, 1.0 micron FIFO.
Virtuoso (Cadence's Layout Editor) is installed and operational. Basic technology files for MOSIS technologies including the HP 0.8um process are on-line. Custom layout and the importation of cells has been tested. Design rule checking in the layout tool is being developed. We expect to follow this with a full suite of DRC, ERC, and LVS development for the Dracula tool set of Cadence.
The decision to use the 8000 series processor has freed us to choose the standard cell place and route tool best for the design effort. Consequently, Cascade has been chosen due to its high degree of integration, supported library availability, and willingness to work with us. Cascade includes not only data-path and control place and route, but also parameterized memories. We are working with Cascade to create a parameterized CAM. This is an interesting opportunity to investigate a CAM which can be rubber-band stretched into different shapes during place and route. The first and second integrated circuits of the project are examining this technology as currently planned.
Synthesis and Simulation using VHDL with Synopsys has been demonstrated. The capabilities and limitations of the Synopsys tool set are being examined. Libraries linking Synopsys to Cascade will soon be completed. This will complete the installation of high-end design capability.
The Cadence tool Allegro is installed and operational. A prototype Protocol Processing Engine (PPE), our intelligent network interface, is being created using this tool to design the printed circuit board.
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