In the Avalanche project, we are designing a multiprocessor memory and communication architecture that significantly reduces the major impediment to scalable parallel computing as we see it, end-to-end communication latency. Our goal is to attack latency in all of its forms for both distributed shared memory and message passing applications. Since the project's inception in 1994, we have been developing a sophisticated multiprocessor simulation environment and using it to evaluate a wide spectrum of design space options for attacking the multiprocessor communication latency problem. To reduce the impact of latency on distributed shared memory applications, we are exploring a variety of techniques for reducing the frequency of cache misses, including support for multiple consistency protocols in hardware, and in particular a novel multi-writer write-update protocol. We are also exploring ways to overlap consistency management operations with computation and communication to hide its overhead. On the message passing front, we are designing an integrated memory and communication controller that will allow incoming data to be placed in any level of the memory hierarchy (from main memory to the first level cache). We are also designing a novel message passing API that reduces the amount of data copying and OS overhead required to exchange messages. Both of these efforts are beginning to bear fruit as we evaluate our design options, and we remain on target to fab our cache and communication control unit in early 1996.
Underlying these major architectural design efforts are several important infrastructure efforts, including: the continuing improvement of our multiprocessor simulation environment and simulation models, the development of an integrated VLSI tool suite based largely on COTS vendor tools, and the development of verification tools so that we can formally evaluate and verify the many concurrent protocols that will be used in Avalanche.
We made one major change of direction in April 1995. After extensive consultations with our corporate partner, Hewlett-Packard, and ARPA, we are retargeting our design efforts from a modified version of the PA-RISC 7100 to the PA-RISC 8000, which HP has announced will be available in 1Q96. As with most major design changes, there are both good and bad points to the change, but the good points clearly outnumber the bad. On the positive side, we will not be required to use HP's dated (and no longer supported) VLSI tools to modify an old design. We are now planning to use commercial VHDL-based tools, which should significantly simplify our VLSI design efforts. The change also means that the Avalanche prototype will be based on a contemporary microprocessor, which should increase the commercial interest in our work. The downside is that the PA-8000 is significantly more complex than the PA-7100 (e.g., it is 4-way superscalar, incorporates a 56-entry instruction reorder buffer, and has two concurrent load/store units). The change to the PA-8000 will necessitate extensive modification of our multiprocessor simulation engine and will add to our learning curve. These concerns notwithstanding, the net effect of moving to the PA-8000 will be very positive.
This report describes in brief our progress from the inception of the project in November 1994 until April 1995. Further details are available in separate technical reports or by contacting the Principal Investigators. The remainder of this report describes in greater detail the following work: the multiprocessor simulation engine, the context-sensitive cache and communication unit (CSCCU) design options with some preliminary simulation results, our message passing hardware and software support, the network interconnect simulation efforts, our initial VLSI tool creation and design efforts, and our protocol verification efforts.
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