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Avalanche: Communication and Memory Architecture for Scalable Parallel Computing

  • Overview
  • Multiprocessor Simulation Engine Design
  • Cache and Communication Control Unit Design
  • Support for Efficient Message Passing
  • Interconnect Simulation Effort
  • VLSI Effort
  • Verification Effort
  • References
    • This work was sponsored by the Space and Naval Warfare Systems Command (SPAWAR) and Advanced Research Projects Agency (ARPA), Communication and Memory Architectures for Scalable Parallel Computing, ARPA order #B990 under SPAWAR contract #N00039-95-C-0018
    Back to the Avalanche Project Home Page, or Computer Science Department Home Page.
    Feedback to <avalanche@jensen.cs.utah.edu>.

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