Avalanche Message Passing
Goals
Approach
SBP Basics
Notifications
SBP Advantages
Direct Deposit (DD) -- A Sample SBP
Bandwidth
The Shared Buffer and Message Passing
The Cache Controller and Message Passing
Conclusions
Results
Bandwidth/Latency @160MHZ
PPE Organization
Sender Based Protocols
Sending A Message
Receiving a Message
Receiving a Message 2
"PAINT" -- The Avalanche Simulation Environment
Outline
Components
Mint Basics
Mint Basics:
Utah Enhancements
Current State
Remaining Work
DSM Taxonomy
The Avalanche Node Architecture
Processor Characteristics
Cache Characteristics
Runway Bus
Coherency Support
The HOST/MMC
Difficulties Associated with the Host System
Avalanche Distributed Shared Memory (DSM)
DSM Problems
Second Order Problems
Leading to a Solution, a Problem, and an Opportunity
Lower Level Performance Solutions
DSM Transaction Examples
Conclusions
Shared Memory Architectures
Summary
Simple Coma
Attraction Memory
Fine Grain Access Control
Memory Access
DSM Model Comparison
CC-NUMA Memory Model
S-COMA Memory Model
Cache Controller
Cache Controller - Occupancy
Cache Controller - Occupancy
Directory Controller - Occupancy
Directory Controller - Occupancy
Directory Controller - Occupancy 2
Directory Controller - Occupancy 2
Directory Controller
Directory Controller State Machine
Cache Controller State Machine
This work was sponsored by
the Space and Naval Warfare Systems Command (SPAWAR) and
Advanced Research Projects Agency (ARPA),
Communication and Memory Architectures for
Scalable Parallel Computing,
ARPA order #B990 under SPAWAR contract #N00039-95-C-0018.
Feedback to <avalanche@jensen.cs.utah.edu>.
Last modified around March 11, 1996.