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Spring 2009

  1. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach (ISCA 08)
  2. Coordinated Management of Mutiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach (MICRO 08)
  3. Dependence-Aware Transactional Memory for Increased Concurrency (MICRO 08)
  4. Design and Evaluation of Hierarchical On-Chip Network Topologies for next generation CMPs (HPCA 09)
  5. BENoC: A Bus Enhanced Network on-chip for a power efficient CMP (CAL July-Dec 2008)
  6. Intra-Disk Parallelism: An Idea Whose Time Has Come (ISCA 08)
  7. Understanding and Designing New Server Architectures for Emerging Warehouse-Computing Environments(ISCA 08)
  8. Lightweight Predication Support for Out of Order Processors (HPCA-09)
  9. Criticality-Based Optimizations for Efficient Load Processing (HPCA-09)
  10. Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency (MICRO-08)
  11. A Comprehensive approach to DRAM power management (HPCA-08)
  12. A Memory-Level Parallelism Aware Fetch Policy for SMT Processors (HPCA 07)
  13. An Adaptive Resource Partitioning Algorithm in SMT Processors (PACT 08)
  14. Larrabee: A Many-Core x86 Architecture for Visual Computing (SIGGRAPH 2008)

Fall 2008

  1. Scavenger: A New Last Level Cache Architecture with Global Block Priority,MICRO 2007
  2. Cache Bursts: A New Approach for Eliminating Dead Blocks and Increasing Cache Efficiency, MICRO 2008
  3. Operating System Power Minimization through Run-time Processor Resource Adaptation, Microprocessors and Microsystems, June 2006
  4. Polymorphic On-Chip Networks, ISCA 08
  5. The Adaptive Transactional Memory Test Platform: A Tool for Experimenting with Transactional Code for Rock
  6. Applications of the Adaptive Transactional Memory Test Platform, Transact, February 23, 2008
  7. Designing An Efficient Kernel-level and User-level Hybrid Approach for MPI Intra-node Communication on Multi-core Systems, Int'l Conference on Parallel Processing (ICPP) 2008
  8. Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors, MICRO 2007
  9. Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems, 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA '08

Spring 2008

  1. Ultra Low-Cost Defect Protection for Microprocessor Pipelines
  2. Gaining Insights into Multicore Cache Partitioning: Bridging the Gap between Simulation and Real Systems
  3. FPGA - Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators, MICRO '07
  4. QoS Policies and Architecture for Cache/Memory in CMP Platforms, SIGMETRICS '07
  5. Penelope: The NBTI-Aware Processor, MICRO '07
  6. The PARSEC Benchmark Suite, Tutorial @ISCA '08
  7. Molecular Caches: A Caching Structure for Dynamic Creation of Application-Specific Heterogeneous Cache Regions, MICRO '06
  8. Adaptive Set Pinning: Managing Shared Caches in Chip Multiprocessors, ASPLOS '08
  9. Process Variation Tolerant 3T1D-Based Cache Architectures, MICRO '07
  10. Flexible Decoupled Transactional Memory Support, ISCA '08
  11. Using Hardware Memory Protection to Build a High-Performance, Strongly Atomic Hybrid Transactional Memory, ISCA '08, presentation slide
  12. 3D-Stacked Memory Architectures for Multi-Core Processors, ISCA '08

Fall 2007

  1. MetaTM/TxLinux: Transactional Memory For An Operating System, H. E. Ramadan, C. J. Rossbach, D. E. Porter, O. S. Hofmann, A. Bhandari, E. Witchel (ISCA 07)
  2. Adaptive Caching: Effective Shaping of Cache Behavior to Workloads , R. Subramanian, Y. Samaragdakis, and G. H. Loh (MICRO 06)
  3. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches, M. K. Qureshi and Yale N. Patt (MICRO 06)
  4. Application Driven Embedded System Design: A Face Recognition Case Study, K. Ramani and Al Davis, CASES Practice Talk
  5. On-Chip Process Variation Detection using Slew-Rate Monitoring Circuit in Sub-100nm CMOS Technology, Amlan Ghosh, Rahul M. Rao, Jae-joon Kim, Richard B. Brown and Ching-Te Chuang (IEEE VLSI Design 2008)
  6. The Landscape of Parallel Computing Research: A View from Berkeley, Krste Asanovic, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams and Katherine A. Yelick (UCB Technical Report)
  7. Feedback Directed Prefetching, Santhosh Srinath, Onur Mutlu, Hyesoon Kim, and Yale N. Patt (HPCA 2007)
  8. Performance Pathologies in Hardware Transactional Memory, Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, David A. Wood (ISCA 2007)
  9. Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware, Smruti Sarangi, Abhishek Tiwari, Josep Torrellas, University of Illinois at Urbana-Champaign (MICRO 2006)
  10. Narrow Width Dynamic Scheduling, Erika Gunadi and Mikko H. Lipasti (Journal of Instruction Level Parallelism Vol. 9)
  11. ParallAX: An Architecture for Real-Time Physics, Thomas Y. Yeh, Petros Faloutsos, Sanjay Patel, Glenn Reinman, UCLA & AGEIA Technologies Inc. (ISCA 2007)
  12. Leveraging 3D Technology for Improved Reliability, N. Madan and R. Balasubramonian
  13. Ultra Low-Cost Defect Protection For Microprocessor Pipelines, Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd Austin (ASPLOS 2006)

Summer 2007

  1. Rotary Router: An Efficient Architecture for CMP Interconnection Networks, ISCA '07
  2. Last Touch Correlated Data Streaming , ISPASS '07
  3. Recycle: Pipeline Adaptation to Tolerate Process Variation, ISCA '07
  4. A Novel Dimensionally Decomposed Router for On-Chip Communication in 3D Architectures, ISCA '07
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Page last modified on September 10, 2009, at 11:14 AM