ACK - An Asynchronous Design Framework
Synthesized Circuit
Structural VHDL Gate Netlist (Greatest Common Divisor)
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
package CONV_PACK_gcd is
-- define attributes
attribute ENUM_ENCODING : STRING;
end CONV_PACK_gcd;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd is
port( reset, gout_0_out, start : in std_logic; gout_0_in1 : out std_logic;
a_tempvar, b_tempvar : in std_logic_vector (7 downto 0); a_1_out,
b_2_out : in std_logic; gout_tempvar : out std_logic_vector (7 downto
0); a_1_in2, b_2_in2 : out std_logic);
end gcd;
architecture SYN_gcd_behv of gcd is
component std_select_0
port( req, sel : in std_logic; true, false : out std_logic);
end component;
component gcd_y
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout :
out std_logic_vector (0 to 7));
end component;
component gcd_pab0_delay
port( pab0_ack : out std_logic; pab0_req : in std_logic);
end component;
component gcd_x_mux0
port( gcd_x_mux_input_0 : in std_logic_vector (0 to 7); gcd_x_mux_set_1
: in std_logic; gcd_x_mux_input_1 : in std_logic_vector (0 to 7);
gcd_x_mux_output : out std_logic_vector (0 to 7));
end component;
component std_select_1
port( req, sel : in std_logic; true, false : out std_logic);
end component;
component gcd_x
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout :
out std_logic_vector (0 to 7));
end component;
component std_xor2_1
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component gcd_gout_tempvar_var_delay
port( gout_tempvar_loaddone, latch : out std_logic; gout_tempvar_load :
in std_logic);
end component;
component std_xor2_0
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component gcd_y_mux0
port( gcd_y_mux_input_0 : in std_logic_vector (0 to 7); gcd_y_mux_set_1
: in std_logic; gcd_y_mux_input_1 : in std_logic_vector (0 to 7);
gcd_y_mux_output : out std_logic_vector (0 to 7));
end component;
component gcd_pab1_delay
port( pab1_ack : out std_logic; pab1_req : in std_logic);
end component;
component gcd_fab4_delay
port( fab4_ack : out std_logic; fab4_req : in std_logic);
end component;
component gcd_gout_tempvar
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout :
out std_logic_vector (0 to 7));
end component;
component gcd_fab4
port( y, x : in std_logic_vector (0 to 7); y_out : out std_logic_vector
(0 to 7));
end component;
component gcd_x_loaddone_ism
port( RESET, xldd, sel1t, sel0t : in std_logic; gcdxldd, processxldd :
out std_logic);
end component;
component gcd_fab3
port( x, y : in std_logic_vector (0 to 7); x_out : out std_logic_vector
(0 to 7));
end component;
component gcd_pab0
port( x, y : in std_logic_vector (0 to 7); select0_select : out
std_logic);
end component;
component gcd_pab1
port( x, y : in std_logic_vector (0 to 7); select1_select : out
std_logic);
end component;
component gcd_x_var_delay
port( latch, x_loaddone : out std_logic; x_load : in std_logic);
end component;
component gcd_y_loaddone_ism
port( RESET, yldd, sel1f, sel0t : in std_logic; gcdyldd, processyldd :
out std_logic);
end component;
component gcd_y_var_delay
port( latch, y_loaddone : out std_logic; y_load : in std_logic);
end component;
component gcd_gcd
port( RESET, start, sel0t, sel0f, gouttvldd, gout0out, gcdyldd, gcdxldd,
gcdwhilereq, b2out, a1out : in std_logic; a1in2, b2in2, gout0in1,
gouttvld, processprocessreq, sel0req, xldx0, yldx0 : out std_logic
);
end component;
component gcd_process
port( RESET, sel1t, sel1f, processyldd, processxldd, processprocessreq,
fab4ack, fab3ack : in std_logic; fab3req, fab4req, gcdwhilereq,
gcdxsm1, gcdysm1, sel1req, xldx1, yldx1 : out std_logic);
end component;
component gcd_fab3_delay
port( fab3_ack : out std_logic; fab3_req : in std_logic);
end component;
signal gcd_y_mux0_gcd_y_mux_output_4, gcd_y_mux0_gcd_y_mux_output_3,
gcd_y_mux0_gcd_y_mux_output_2, gcd_fab3_x_out_0, gcd_fab3_x_out_1,
gcd_y_mux0_gcd_y_mux_output_1, gcd_fab3_x_out_2,
gcd_y_mux0_gcd_y_mux_output_0, gcd_fab3_x_out_3, gcd_fab3_x_out_4,
gcd_fab3_x_out_5, gcd_fab3_x_out_6, gcd_fab3_x_out_7,
select1_select_select1_true, gcd_y_var_delay_latch,
gcd_pab0_delay_pab0_ack, gcd_pab0_select0_select, gcd_x_variable_dout_0,
gcd_x_variable_dout_1, gcd_fab4_delay_fab4_ack, gcd_x_variable_dout_2,
gcd_x_variable_dout_3, gcd_x_variable_dout_4, gcd_x_variable_dout_5,
gcd_x_variable_dout_6, gcd_x_variable_dout_7, gcd_x_var_delay_x_loaddone,
select0_select_select0_false, gcd_gcd_processprocessreq,
gcd_gout_tempvar_var_delay_latch, gcd_process_gcdwhilereq,
gcd_process_gcdysm1, gcd_process_gcdxsm1, select1_select_select1_false,
xor1_xor_x_load, gcd_x_loaddone_ism_processxldd, gcd_y_variable_dout_7,
xor0_xor_y_load, gcd_y_variable_dout_6, gcd_y_variable_dout_5,
gcd_y_variable_dout_4, gcd_y_variable_dout_3, gcd_y_variable_dout_2,
gcd_y_variable_dout_1, gcd_y_variable_dout_0, select0_select_select0_true
, gcd_pab1_delay_pab1_ack, gcd_x_mux0_gcd_x_mux_output_0,
gcd_x_mux0_gcd_x_mux_output_1, gcd_x_mux0_gcd_x_mux_output_2,
gcd_x_mux0_gcd_x_mux_output_3, gcd_x_mux0_gcd_x_mux_output_4,
gcd_x_mux0_gcd_x_mux_output_5, gcd_x_mux0_gcd_x_mux_output_6,
gcd_x_mux0_gcd_x_mux_output_7, gcd_gcd_yldx0, gcd_gcd_xldx0,
gcd_process_sel1req, gcd_process_fab3req, gcd_pab1_select1_select,
gcd_y_loaddone_ism_gcdyldd, gcd_fab3_delay_fab3_ack,
gcd_y_loaddone_ism_processyldd, gcd_x_var_delay_latch, gcd_gcd_gouttvld,
gcd_gcd_sel0req, gcd_y_var_delay_y_loaddone, gcd_fab4_y_out_7,
gcd_fab4_y_out_6, gcd_fab4_y_out_5, gcd_process_xldx1, gcd_fab4_y_out_4,
gcd_fab4_y_out_3, gcd_process_yldx1, gcd_fab4_y_out_2, gcd_fab4_y_out_1,
gcd_x_loaddone_ism_gcdxldd, gcd_fab4_y_out_0,
gcd_gout_tempvar_var_delay_gout_tempvar_loaddone, gcd_process_fab4req,
gcd_y_mux0_gcd_y_mux_output_7, gcd_y_mux0_gcd_y_mux_output_6,
gcd_y_mux0_gcd_y_mux_output_5 : std_logic;
begin
I_0 : std_xor2_1 port map( IN0 => gcd_gcd_xldx0, IN1 => gcd_process_xldx1, Y
=> xor1_xor_x_load);
I_1 : gcd_gcd port map( RESET => reset, start => start, sel0t =>
select0_select_select0_true, sel0f =>
select0_select_select0_false, gouttvldd =>
gcd_gout_tempvar_var_delay_gout_tempvar_loaddone,
gout0out => gout_0_out, gcdyldd =>
gcd_y_loaddone_ism_gcdyldd, gcdxldd =>
gcd_x_loaddone_ism_gcdxldd, gcdwhilereq =>
gcd_process_gcdwhilereq, b2out => b_2_out, a1out =>
a_1_out, a1in2 => a_1_in2, b2in2 => b_2_in2,
gout0in1 => gout_0_in1, gouttvld => gcd_gcd_gouttvld
, processprocessreq => gcd_gcd_processprocessreq,
sel0req => gcd_gcd_sel0req, xldx0 => gcd_gcd_xldx0,
yldx0 => gcd_gcd_yldx0);
I_2 : gcd_x port map( din(0) => gcd_x_mux0_gcd_x_mux_output_7, din(1) =>
gcd_x_mux0_gcd_x_mux_output_6, din(2) =>
gcd_x_mux0_gcd_x_mux_output_5, din(3) =>
gcd_x_mux0_gcd_x_mux_output_4, din(4) =>
gcd_x_mux0_gcd_x_mux_output_3, din(5) =>
gcd_x_mux0_gcd_x_mux_output_2, din(6) =>
gcd_x_mux0_gcd_x_mux_output_1, din(7) =>
gcd_x_mux0_gcd_x_mux_output_0, latch =>
gcd_x_var_delay_latch, dout(0) =>
gcd_x_variable_dout_7, dout(1) =>
gcd_x_variable_dout_6, dout(2) =>
gcd_x_variable_dout_5, dout(3) =>
gcd_x_variable_dout_4, dout(4) =>
gcd_x_variable_dout_3, dout(5) =>
gcd_x_variable_dout_2, dout(6) =>
gcd_x_variable_dout_1, dout(7) =>
gcd_x_variable_dout_0);
I_3 : gcd_y port map( din(0) => gcd_y_mux0_gcd_y_mux_output_7, din(1) =>
gcd_y_mux0_gcd_y_mux_output_6, din(2) =>
gcd_y_mux0_gcd_y_mux_output_5, din(3) =>
gcd_y_mux0_gcd_y_mux_output_4, din(4) =>
gcd_y_mux0_gcd_y_mux_output_3, din(5) =>
gcd_y_mux0_gcd_y_mux_output_2, din(6) =>
gcd_y_mux0_gcd_y_mux_output_1, din(7) =>
gcd_y_mux0_gcd_y_mux_output_0, latch =>
gcd_y_var_delay_latch, dout(0) =>
gcd_y_variable_dout_7, dout(1) =>
gcd_y_variable_dout_6, dout(2) =>
gcd_y_variable_dout_5, dout(3) =>
gcd_y_variable_dout_4, dout(4) =>
gcd_y_variable_dout_3, dout(5) =>
gcd_y_variable_dout_2, dout(6) =>
gcd_y_variable_dout_1, dout(7) =>
gcd_y_variable_dout_0);
I_4 : gcd_gout_tempvar port map( din(0) => gcd_x_variable_dout_7, din(1) =>
gcd_x_variable_dout_6, din(2) =>
gcd_x_variable_dout_5, din(3) =>
gcd_x_variable_dout_4, din(4) =>
gcd_x_variable_dout_3, din(5) =>
gcd_x_variable_dout_2, din(6) =>
gcd_x_variable_dout_1, din(7) =>
gcd_x_variable_dout_0, latch =>
gcd_gout_tempvar_var_delay_latch, dout(0) =>
gout_tempvar(7), dout(1) => gout_tempvar(6), dout(2)
=> gout_tempvar(5), dout(3) => gout_tempvar(4),
dout(4) => gout_tempvar(3), dout(5) =>
gout_tempvar(2), dout(6) => gout_tempvar(1), dout(7)
=> gout_tempvar(0));
I_5 : std_select_1 port map( req => gcd_pab0_delay_pab0_ack, sel =>
gcd_pab0_select0_select, true =>
select0_select_select0_true, false =>
select0_select_select0_false);
I_6 : std_select_0 port map( req => gcd_pab1_delay_pab1_ack, sel =>
gcd_pab1_select1_select, true =>
select1_select_select1_true, false =>
select1_select_select1_false);
I_7 : gcd_fab3 port map( x(0) => gcd_x_variable_dout_7, x(1) =>
gcd_x_variable_dout_6, x(2) => gcd_x_variable_dout_5
, x(3) => gcd_x_variable_dout_4, x(4) =>
gcd_x_variable_dout_3, x(5) => gcd_x_variable_dout_2
, x(6) => gcd_x_variable_dout_1, x(7) =>
gcd_x_variable_dout_0, y(0) => gcd_y_variable_dout_7
, y(1) => gcd_y_variable_dout_6, y(2) =>
gcd_y_variable_dout_5, y(3) => gcd_y_variable_dout_4
, y(4) => gcd_y_variable_dout_3, y(5) =>
gcd_y_variable_dout_2, y(6) => gcd_y_variable_dout_1
, y(7) => gcd_y_variable_dout_0, x_out(0) =>
gcd_fab3_x_out_7, x_out(1) => gcd_fab3_x_out_6,
x_out(2) => gcd_fab3_x_out_5, x_out(3) =>
gcd_fab3_x_out_4, x_out(4) => gcd_fab3_x_out_3,
x_out(5) => gcd_fab3_x_out_2, x_out(6) =>
gcd_fab3_x_out_1, x_out(7) => gcd_fab3_x_out_0);
I_8 : gcd_fab4 port map( y(0) => gcd_y_variable_dout_7, y(1) =>
gcd_y_variable_dout_6, y(2) => gcd_y_variable_dout_5
, y(3) => gcd_y_variable_dout_4, y(4) =>
gcd_y_variable_dout_3, y(5) => gcd_y_variable_dout_2
, y(6) => gcd_y_variable_dout_1, y(7) =>
gcd_y_variable_dout_0, x(0) => gcd_x_variable_dout_7
, x(1) => gcd_x_variable_dout_6, x(2) =>
gcd_x_variable_dout_5, x(3) => gcd_x_variable_dout_4
, x(4) => gcd_x_variable_dout_3, x(5) =>
gcd_x_variable_dout_2, x(6) => gcd_x_variable_dout_1
, x(7) => gcd_x_variable_dout_0, y_out(0) =>
gcd_fab4_y_out_7, y_out(1) => gcd_fab4_y_out_6,
y_out(2) => gcd_fab4_y_out_5, y_out(3) =>
gcd_fab4_y_out_4, y_out(4) => gcd_fab4_y_out_3,
y_out(5) => gcd_fab4_y_out_2, y_out(6) =>
gcd_fab4_y_out_1, y_out(7) => gcd_fab4_y_out_0);
I_9 : gcd_fab3_delay port map( fab3_ack => gcd_fab3_delay_fab3_ack, fab3_req
=> gcd_process_fab3req);
I_19 : gcd_x_mux0 port map( gcd_x_mux_input_0(0) => a_tempvar(7),
gcd_x_mux_input_0(1) => a_tempvar(6),
gcd_x_mux_input_0(2) => a_tempvar(5),
gcd_x_mux_input_0(3) => a_tempvar(4),
gcd_x_mux_input_0(4) => a_tempvar(3),
gcd_x_mux_input_0(5) => a_tempvar(2),
gcd_x_mux_input_0(6) => a_tempvar(1),
gcd_x_mux_input_0(7) => a_tempvar(0),
gcd_x_mux_set_1 => gcd_process_gcdxsm1,
gcd_x_mux_input_1(0) => gcd_fab3_x_out_7,
gcd_x_mux_input_1(1) => gcd_fab3_x_out_6,
gcd_x_mux_input_1(2) => gcd_fab3_x_out_5,
gcd_x_mux_input_1(3) => gcd_fab3_x_out_4,
gcd_x_mux_input_1(4) => gcd_fab3_x_out_3,
gcd_x_mux_input_1(5) => gcd_fab3_x_out_2,
gcd_x_mux_input_1(6) => gcd_fab3_x_out_1,
gcd_x_mux_input_1(7) => gcd_fab3_x_out_0,
gcd_x_mux_output(0) => gcd_x_mux0_gcd_x_mux_output_7
, gcd_x_mux_output(1) =>
gcd_x_mux0_gcd_x_mux_output_6, gcd_x_mux_output(2)
=> gcd_x_mux0_gcd_x_mux_output_5,
gcd_x_mux_output(3) => gcd_x_mux0_gcd_x_mux_output_4
, gcd_x_mux_output(4) =>
gcd_x_mux0_gcd_x_mux_output_3, gcd_x_mux_output(5)
=> gcd_x_mux0_gcd_x_mux_output_2,
gcd_x_mux_output(6) => gcd_x_mux0_gcd_x_mux_output_1
, gcd_x_mux_output(7) =>
gcd_x_mux0_gcd_x_mux_output_0);
I_18 : gcd_process port map( RESET => reset, sel1t =>
select1_select_select1_true, sel1f =>
select1_select_select1_false, processyldd =>
gcd_y_loaddone_ism_processyldd, processxldd =>
gcd_x_loaddone_ism_processxldd, processprocessreq =>
gcd_gcd_processprocessreq, fab4ack =>
gcd_fab4_delay_fab4_ack, fab3ack =>
gcd_fab3_delay_fab3_ack, fab3req =>
gcd_process_fab3req, fab4req => gcd_process_fab4req,
gcdwhilereq => gcd_process_gcdwhilereq, gcdxsm1 =>
gcd_process_gcdxsm1, gcdysm1 => gcd_process_gcdysm1,
sel1req => gcd_process_sel1req, xldx1 =>
gcd_process_xldx1, yldx1 => gcd_process_yldx1);
I_17 : gcd_gout_tempvar_var_delay port map( gout_tempvar_loaddone =>
gcd_gout_tempvar_var_delay_gout_tempvar_loaddone,
latch => gcd_gout_tempvar_var_delay_latch,
gout_tempvar_load => gcd_gcd_gouttvld);
I_16 : gcd_pab1_delay port map( pab1_ack => gcd_pab1_delay_pab1_ack,
pab1_req => gcd_process_sel1req);
I_15 : gcd_pab0_delay port map( pab0_ack => gcd_pab0_delay_pab0_ack,
pab0_req => gcd_gcd_sel0req);
I_13 : gcd_pab1 port map( x(0) => gcd_x_variable_dout_7, x(1) =>
gcd_x_variable_dout_6, x(2) => gcd_x_variable_dout_5
, x(3) => gcd_x_variable_dout_4, x(4) =>
gcd_x_variable_dout_3, x(5) => gcd_x_variable_dout_2
, x(6) => gcd_x_variable_dout_1, x(7) =>
gcd_x_variable_dout_0, y(0) => gcd_y_variable_dout_7
, y(1) => gcd_y_variable_dout_6, y(2) =>
gcd_y_variable_dout_5, y(3) => gcd_y_variable_dout_4
, y(4) => gcd_y_variable_dout_3, y(5) =>
gcd_y_variable_dout_2, y(6) => gcd_y_variable_dout_1
, y(7) => gcd_y_variable_dout_0, select1_select =>
gcd_pab1_select1_select);
I_12 : gcd_pab0 port map( x(0) => gcd_x_variable_dout_7, x(1) =>
gcd_x_variable_dout_6, x(2) => gcd_x_variable_dout_5
, x(3) => gcd_x_variable_dout_4, x(4) =>
gcd_x_variable_dout_3, x(5) => gcd_x_variable_dout_2
, x(6) => gcd_x_variable_dout_1, x(7) =>
gcd_x_variable_dout_0, y(0) => gcd_y_variable_dout_7
, y(1) => gcd_y_variable_dout_6, y(2) =>
gcd_y_variable_dout_5, y(3) => gcd_y_variable_dout_4
, y(4) => gcd_y_variable_dout_3, y(5) =>
gcd_y_variable_dout_2, y(6) => gcd_y_variable_dout_1
, y(7) => gcd_y_variable_dout_0, select0_select =>
gcd_pab0_select0_select);
I_11 : gcd_fab4_delay port map( fab4_ack => gcd_fab4_delay_fab4_ack,
fab4_req => gcd_process_fab4req);
I_10 : gcd_y_mux0 port map( gcd_y_mux_input_0(0) => b_tempvar(7),
gcd_y_mux_input_0(1) => b_tempvar(6),
gcd_y_mux_input_0(2) => b_tempvar(5),
gcd_y_mux_input_0(3) => b_tempvar(4),
gcd_y_mux_input_0(4) => b_tempvar(3),
gcd_y_mux_input_0(5) => b_tempvar(2),
gcd_y_mux_input_0(6) => b_tempvar(1),
gcd_y_mux_input_0(7) => b_tempvar(0),
gcd_y_mux_set_1 => gcd_process_gcdysm1,
gcd_y_mux_input_1(0) => gcd_fab4_y_out_7,
gcd_y_mux_input_1(1) => gcd_fab4_y_out_6,
gcd_y_mux_input_1(2) => gcd_fab4_y_out_5,
gcd_y_mux_input_1(3) => gcd_fab4_y_out_4,
gcd_y_mux_input_1(4) => gcd_fab4_y_out_3,
gcd_y_mux_input_1(5) => gcd_fab4_y_out_2,
gcd_y_mux_input_1(6) => gcd_fab4_y_out_1,
gcd_y_mux_input_1(7) => gcd_fab4_y_out_0,
gcd_y_mux_output(0) => gcd_y_mux0_gcd_y_mux_output_7
, gcd_y_mux_output(1) =>
gcd_y_mux0_gcd_y_mux_output_6, gcd_y_mux_output(2)
=> gcd_y_mux0_gcd_y_mux_output_5,
gcd_y_mux_output(3) => gcd_y_mux0_gcd_y_mux_output_4
, gcd_y_mux_output(4) =>
gcd_y_mux0_gcd_y_mux_output_3, gcd_y_mux_output(5)
=> gcd_y_mux0_gcd_y_mux_output_2,
gcd_y_mux_output(6) => gcd_y_mux0_gcd_y_mux_output_1
, gcd_y_mux_output(7) =>
gcd_y_mux0_gcd_y_mux_output_0);
I_23 : std_xor2_0 port map( IN0 => gcd_gcd_yldx0, IN1 => gcd_process_yldx1,
Y => xor0_xor_y_load);
I_21 : gcd_y_var_delay port map( latch => gcd_y_var_delay_latch, y_loaddone
=> gcd_y_var_delay_y_loaddone, y_load =>
xor0_xor_y_load);
I_20 : gcd_x_var_delay port map( latch => gcd_x_var_delay_latch, x_loaddone
=> gcd_x_var_delay_x_loaddone, x_load =>
xor1_xor_x_load);
I_1I_14 : gcd_x_loaddone_ism port map( RESET => reset, xldd =>
gcd_x_var_delay_x_loaddone, sel1t =>
select1_select_select1_true, sel0t =>
select0_select_select0_true, gcdxldd =>
gcd_x_loaddone_ism_gcdxldd, processxldd =>
gcd_x_loaddone_ism_processxldd);
I_2I_22 : gcd_y_loaddone_ism port map( RESET => reset, yldd =>
gcd_y_var_delay_y_loaddone, sel1f =>
select1_select_select1_false, sel0t =>
select0_select_select0_true, gcdyldd =>
gcd_y_loaddone_ism_gcdyldd, processyldd =>
gcd_y_loaddone_ism_processyldd);
end SYN_gcd_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_inv_1 is
port( IN0 : in std_logic; Y : out std_logic);
end std_inv_1;
architecture SYN_std_inv_behv_1 of std_inv_1 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_std_inv_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_inv_0 is
port( IN0 : in std_logic; Y : out std_logic);
end std_inv_0;
architecture SYN_std_inv_behv_0 of std_inv_0 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_std_inv_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_3 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_3;
architecture SYN_std_mux2_behv_3 of std_mux2_3 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_2 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_2;
architecture SYN_std_mux2_behv_2 of std_mux2_2 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_1 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_1;
architecture SYN_std_mux2_behv_1 of std_mux2_1 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_0 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_0;
architecture SYN_std_mux2_behv_0 of std_mux2_0 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_select_0 is
port( req, sel : in std_logic; true, false : out std_logic);
end std_select_0;
architecture SYN_std_select_behv_0 of std_select_0 is
component std_inv_1
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_inv_0
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_mux2_3
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_2
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_1
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_0
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
signal net2i, net0, net1, net2, net3, net0i : std_logic;
begin
true <= net1;
false <= net0;
I_0 : std_mux2_3 port map( IN0 => net2i, IN1 => net3, SEL => req, Y => net0)
;
I_1 : std_mux2_2 port map( IN0 => net2, IN1 => net3, SEL => req, Y => net1);
I_2 : std_mux2_1 port map( IN0 => net0i, IN1 => net1, SEL => sel, Y => net2)
;
I_3 : std_mux2_0 port map( IN0 => net0, IN1 => net1, SEL => sel, Y => net3);
I_4 : std_inv_1 port map( IN0 => net2, Y => net2i);
I_5 : std_inv_0 port map( IN0 => net0, Y => net0i);
end SYN_std_select_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_y is
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout : out
std_logic_vector (0 to 7));
end gcd_y;
architecture SYN_gcd_y_behv of gcd_y is
component stddff_2x
port( CLK, D : in std_logic; Q : out std_logic);
end component;
component stddff
port( CLK, D : in std_logic; Q : out std_logic);
end component;
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal n37 : std_logic;
begin
U8 : stdbuf_2x port map( IN0 => latch, Y => n37);
dout_reg_0 : stddff port map( CLK => n37, D => din(7), Q => dout(7));
dout_reg_1 : stddff port map( CLK => n37, D => din(6), Q => dout(6));
dout_reg_2 : stddff_2x port map( CLK => n37, D => din(5), Q => dout(5));
dout_reg_3 : stddff port map( CLK => n37, D => din(4), Q => dout(4));
dout_reg_4 : stddff_2x port map( CLK => n37, D => din(3), Q => dout(3));
dout_reg_5 : stddff port map( CLK => n37, D => din(2), Q => dout(2));
dout_reg_6 : stddff port map( CLK => n37, D => din(1), Q => dout(1));
dout_reg_7 : stddff port map( CLK => n37, D => din(0), Q => dout(0));
end SYN_gcd_y_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_42 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_42;
architecture SYN_std_buf_behv_42 of std_buf_42 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_42;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_41 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_41;
architecture SYN_std_buf_behv_41 of std_buf_41 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_41;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_44 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_44;
architecture SYN_std_buf_behv_44 of std_buf_44 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_44;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_43 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_43;
architecture SYN_std_buf_behv_43 of std_buf_43 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_43;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_pab0_delay is
port( pab0_ack : out std_logic; pab0_req : in std_logic);
end gcd_pab0_delay;
architecture SYN_gcd_pab0_delay_behv of gcd_pab0_delay is
component std_buf_42
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_41
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_44
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_43
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal a1, a2, a3 : std_logic;
begin
I_2a : std_buf_44 port map( IN0 => a2, Y => a3);
I_3a : std_buf_43 port map( IN0 => a3, Y => pab0_ack);
I_0 : std_buf_42 port map( IN0 => pab0_req, Y => a1);
I_1a : std_buf_41 port map( IN0 => a1, Y => a2);
end SYN_gcd_pab0_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_x_mux0 is
port( gcd_x_mux_input_0 : in std_logic_vector (0 to 7); gcd_x_mux_set_1 :
in std_logic; gcd_x_mux_input_1 : in std_logic_vector (0 to 7);
gcd_x_mux_output : out std_logic_vector (0 to 7));
end gcd_x_mux0;
architecture SYN_gcd_x_mux0beh of gcd_x_mux0 is
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
signal n35 : std_logic;
begin
U7 : stdbuf_2x port map( IN0 => gcd_x_mux_set_1, Y => n35);
U8 : stdmux2 port map( IN0 => gcd_x_mux_input_0(0), IN1 =>
gcd_x_mux_input_1(0), S0 => n35, Y =>
gcd_x_mux_output(0));
U9 : stdmux2 port map( IN0 => gcd_x_mux_input_0(1), IN1 =>
gcd_x_mux_input_1(1), S0 => n35, Y =>
gcd_x_mux_output(1));
U10 : stdmux2 port map( IN0 => gcd_x_mux_input_0(2), IN1 =>
gcd_x_mux_input_1(2), S0 => n35, Y =>
gcd_x_mux_output(2));
U11 : stdmux2 port map( IN0 => gcd_x_mux_input_0(3), IN1 =>
gcd_x_mux_input_1(3), S0 => n35, Y =>
gcd_x_mux_output(3));
U12 : stdmux2 port map( IN0 => gcd_x_mux_input_0(4), IN1 =>
gcd_x_mux_input_1(4), S0 => n35, Y =>
gcd_x_mux_output(4));
U13 : stdmux2 port map( IN0 => gcd_x_mux_input_0(5), IN1 =>
gcd_x_mux_input_1(5), S0 => n35, Y =>
gcd_x_mux_output(5));
U14 : stdmux2 port map( IN0 => gcd_x_mux_input_0(6), IN1 =>
gcd_x_mux_input_1(6), S0 => n35, Y =>
gcd_x_mux_output(6));
U15 : stdmux2 port map( IN0 => gcd_x_mux_input_0(7), IN1 =>
gcd_x_mux_input_1(7), S0 => n35, Y =>
gcd_x_mux_output(7));
end SYN_gcd_x_mux0beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_inv_3 is
port( IN0 : in std_logic; Y : out std_logic);
end std_inv_3;
architecture SYN_std_inv_behv_3 of std_inv_3 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_std_inv_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_inv_2 is
port( IN0 : in std_logic; Y : out std_logic);
end std_inv_2;
architecture SYN_std_inv_behv_2 of std_inv_2 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_std_inv_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_7 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_7;
architecture SYN_std_mux2_behv_7 of std_mux2_7 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_6 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_6;
architecture SYN_std_mux2_behv_6 of std_mux2_6 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_5 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_5;
architecture SYN_std_mux2_behv_5 of std_mux2_5 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_mux2_4 is
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end std_mux2_4;
architecture SYN_std_mux2_behv_4 of std_mux2_4 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdmux2 port map( IN0 => IN0, IN1 => IN1, S0 => SEL, Y => Y);
end SYN_std_mux2_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_select_1 is
port( req, sel : in std_logic; true, false : out std_logic);
end std_select_1;
architecture SYN_std_select_behv_1 of std_select_1 is
component std_inv_3
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_inv_2
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_mux2_7
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_6
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_5
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
component std_mux2_4
port( IN0, IN1, SEL : in std_logic; Y : out std_logic);
end component;
signal net2i, net0, net1, net2, net3, net0i : std_logic;
begin
true <= net1;
false <= net0;
I_0 : std_mux2_7 port map( IN0 => net2i, IN1 => net3, SEL => req, Y => net0)
;
I_1 : std_mux2_6 port map( IN0 => net2, IN1 => net3, SEL => req, Y => net1);
I_2 : std_mux2_5 port map( IN0 => net0i, IN1 => net1, SEL => sel, Y => net2)
;
I_3 : std_mux2_4 port map( IN0 => net0, IN1 => net1, SEL => sel, Y => net3);
I_4 : std_inv_3 port map( IN0 => net2, Y => net2i);
I_5 : std_inv_2 port map( IN0 => net0, Y => net0i);
end SYN_std_select_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_x is
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout : out
std_logic_vector (0 to 7));
end gcd_x;
architecture SYN_gcd_x_behv of gcd_x is
component stddff_2x
port( CLK, D : in std_logic; Q : out std_logic);
end component;
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal n38 : std_logic;
begin
U8 : stdbuf_2x port map( IN0 => latch, Y => n38);
dout_reg_0 : stddff_2x port map( CLK => n38, D => din(7), Q => dout(7));
dout_reg_1 : stddff_2x port map( CLK => n38, D => din(6), Q => dout(6));
dout_reg_2 : stddff_2x port map( CLK => n38, D => din(5), Q => dout(5));
dout_reg_3 : stddff_2x port map( CLK => n38, D => din(4), Q => dout(4));
dout_reg_4 : stddff_2x port map( CLK => n38, D => din(3), Q => dout(3));
dout_reg_5 : stddff_2x port map( CLK => n38, D => din(2), Q => dout(2));
dout_reg_6 : stddff_2x port map( CLK => n38, D => din(1), Q => dout(1));
dout_reg_7 : stddff_2x port map( CLK => n38, D => din(0), Q => dout(0));
end SYN_gcd_x_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_xor2_1 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end std_xor2_1;
architecture SYN_std_xor2_behv_1 of std_xor2_1 is
component stdxor2_2x
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdxor2_2x port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_std_xor2_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_55 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_55;
architecture SYN_std_buf_behv_55 of std_buf_55 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_55;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_54 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_54;
architecture SYN_std_buf_behv_54 of std_buf_54 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_54;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_53 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_53;
architecture SYN_std_buf_behv_53 of std_buf_53 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_53;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_59 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_59;
architecture SYN_std_buf_behv_59 of std_buf_59 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_59;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_58 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_58;
architecture SYN_std_buf_behv_58 of std_buf_58 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_58;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_57 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_57;
architecture SYN_std_buf_behv_57 of std_buf_57 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_57;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_56 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_56;
architecture SYN_std_buf_behv_56 of std_buf_56 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_56;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_gout_tempvar_var_delay is
port( gout_tempvar_loaddone, latch : out std_logic; gout_tempvar_load : in
std_logic);
end gcd_gout_tempvar_var_delay;
architecture SYN_gcd_gout_tempvar_var_delay_behv of gcd_gout_tempvar_var_delay
is
component std_buf_55
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_54
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_53
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_59
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_58
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_57
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_56
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal l1, a1, a2, a3, a4 : std_logic;
begin
I_2a : std_buf_59 port map( IN0 => a2, Y => a3);
I_3a : std_buf_58 port map( IN0 => a3, Y => a4);
I_4a : std_buf_57 port map( IN0 => a4, Y => gout_tempvar_loaddone);
I_0 : std_buf_56 port map( IN0 => gout_tempvar_load, Y => l1);
I_1 : std_buf_55 port map( IN0 => gout_tempvar_load, Y => a1);
I_1l : std_buf_54 port map( IN0 => l1, Y => latch);
I_1a : std_buf_53 port map( IN0 => a1, Y => a2);
end SYN_gcd_gout_tempvar_var_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_xor2_0 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end std_xor2_0;
architecture SYN_std_xor2_behv_0 of std_xor2_0 is
component stdxor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdxor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_std_xor2_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_y_mux0 is
port( gcd_y_mux_input_0 : in std_logic_vector (0 to 7); gcd_y_mux_set_1 :
in std_logic; gcd_y_mux_input_1 : in std_logic_vector (0 to 7);
gcd_y_mux_output : out std_logic_vector (0 to 7));
end gcd_y_mux0;
architecture SYN_gcd_y_mux0beh of gcd_y_mux0 is
component stdmux2
port( IN0, IN1, S0 : in std_logic; Y : out std_logic);
end component;
begin
U7 : stdmux2 port map( IN0 => gcd_y_mux_input_0(0), IN1 =>
gcd_y_mux_input_1(0), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(0));
U8 : stdmux2 port map( IN0 => gcd_y_mux_input_0(1), IN1 =>
gcd_y_mux_input_1(1), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(1));
U9 : stdmux2 port map( IN0 => gcd_y_mux_input_0(2), IN1 =>
gcd_y_mux_input_1(2), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(2));
U10 : stdmux2 port map( IN0 => gcd_y_mux_input_0(3), IN1 =>
gcd_y_mux_input_1(3), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(3));
U11 : stdmux2 port map( IN0 => gcd_y_mux_input_0(4), IN1 =>
gcd_y_mux_input_1(4), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(4));
U12 : stdmux2 port map( IN0 => gcd_y_mux_input_0(5), IN1 =>
gcd_y_mux_input_1(5), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(5));
U13 : stdmux2 port map( IN0 => gcd_y_mux_input_0(6), IN1 =>
gcd_y_mux_input_1(6), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(6));
U14 : stdmux2 port map( IN0 => gcd_y_mux_input_0(7), IN1 =>
gcd_y_mux_input_1(7), S0 => gcd_y_mux_set_1, Y =>
gcd_y_mux_output(7));
end SYN_gcd_y_mux0beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_52 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_52;
architecture SYN_std_buf_behv_52 of std_buf_52 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_52;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_51 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_51;
architecture SYN_std_buf_behv_51 of std_buf_51 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_51;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_50 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_50;
architecture SYN_std_buf_behv_50 of std_buf_50 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_50;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_49 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_49;
architecture SYN_std_buf_behv_49 of std_buf_49 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_49;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_48 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_48;
architecture SYN_std_buf_behv_48 of std_buf_48 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_48;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_47 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_47;
architecture SYN_std_buf_behv_47 of std_buf_47 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_47;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_46 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_46;
architecture SYN_std_buf_behv_46 of std_buf_46 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_46;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_45 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_45;
architecture SYN_std_buf_behv_45 of std_buf_45 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_45;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_pab1_delay is
port( pab1_ack : out std_logic; pab1_req : in std_logic);
end gcd_pab1_delay;
architecture SYN_gcd_pab1_delay_behv of gcd_pab1_delay is
component std_buf_52
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_51
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_50
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_49
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_48
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_47
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_46
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_45
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal a1, a2, a3, a4, a5, a6, a7 : std_logic;
begin
I_2a : std_buf_52 port map( IN0 => a2, Y => a3);
I_3a : std_buf_51 port map( IN0 => a3, Y => a4);
I_4a : std_buf_50 port map( IN0 => a4, Y => a5);
I_5a : std_buf_49 port map( IN0 => a5, Y => a6);
I_6a : std_buf_48 port map( IN0 => a6, Y => a7);
I_7a : std_buf_47 port map( IN0 => a7, Y => pab1_ack);
I_0 : std_buf_46 port map( IN0 => pab1_req, Y => a1);
I_1a : std_buf_45 port map( IN0 => a1, Y => a2);
end SYN_gcd_pab1_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_40 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_40;
architecture SYN_std_buf_behv_40 of std_buf_40 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_40;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_29 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_29;
architecture SYN_std_buf_behv_29 of std_buf_29 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_29;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_28 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_28;
architecture SYN_std_buf_behv_28 of std_buf_28 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_28;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_27 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_27;
architecture SYN_std_buf_behv_27 of std_buf_27 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_27;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_26 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_26;
architecture SYN_std_buf_behv_26 of std_buf_26 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_26;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_39 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_39;
architecture SYN_std_buf_behv_39 of std_buf_39 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_39;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_25 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_25;
architecture SYN_std_buf_behv_25 of std_buf_25 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_25;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_38 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_38;
architecture SYN_std_buf_behv_38 of std_buf_38 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_38;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_24 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_24;
architecture SYN_std_buf_behv_24 of std_buf_24 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_24;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_37 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_37;
architecture SYN_std_buf_behv_37 of std_buf_37 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_37;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_23 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_23;
architecture SYN_std_buf_behv_23 of std_buf_23 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_23;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_36 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_36;
architecture SYN_std_buf_behv_36 of std_buf_36 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_36;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_22 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_22;
architecture SYN_std_buf_behv_22 of std_buf_22 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_22;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_35 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_35;
architecture SYN_std_buf_behv_35 of std_buf_35 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_35;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_34 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_34;
architecture SYN_std_buf_behv_34 of std_buf_34 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_34;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_21 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_21;
architecture SYN_std_buf_behv_21 of std_buf_21 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_21;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_33 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_33;
architecture SYN_std_buf_behv_33 of std_buf_33 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_33;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_32 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_32;
architecture SYN_std_buf_behv_32 of std_buf_32 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_32;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_31 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_31;
architecture SYN_std_buf_behv_31 of std_buf_31 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_31;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_30 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_30;
architecture SYN_std_buf_behv_30 of std_buf_30 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_30;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab4_delay is
port( fab4_ack : out std_logic; fab4_req : in std_logic);
end gcd_fab4_delay;
architecture SYN_gcd_fab4_delay_behv of gcd_fab4_delay is
component std_buf_40
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_29
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_28
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_27
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_26
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_39
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_25
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_38
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_24
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_37
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_23
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_36
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_22
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_35
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_34
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_21
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_33
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_32
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_31
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_30
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16
, a17, a18, a19 : std_logic;
begin
I_12a : std_buf_40 port map( IN0 => a12, Y => a13);
I_2a : std_buf_39 port map( IN0 => a2, Y => a3);
I_13a : std_buf_38 port map( IN0 => a13, Y => a14);
I_3a : std_buf_37 port map( IN0 => a3, Y => a4);
I_14a : std_buf_36 port map( IN0 => a14, Y => a15);
I_4a : std_buf_35 port map( IN0 => a4, Y => a5);
I_15a : std_buf_34 port map( IN0 => a15, Y => a16);
I_5a : std_buf_33 port map( IN0 => a5, Y => a6);
I_16a : std_buf_32 port map( IN0 => a16, Y => a17);
I_6a : std_buf_31 port map( IN0 => a6, Y => a7);
I_17a : std_buf_30 port map( IN0 => a17, Y => a18);
I_7a : std_buf_29 port map( IN0 => a7, Y => a8);
I_18a : std_buf_28 port map( IN0 => a18, Y => a19);
I_8a : std_buf_27 port map( IN0 => a8, Y => a9);
I_0 : std_buf_26 port map( IN0 => fab4_req, Y => a1);
I_19a : std_buf_25 port map( IN0 => a19, Y => fab4_ack);
I_9a : std_buf_24 port map( IN0 => a9, Y => a10);
I_10a : std_buf_23 port map( IN0 => a10, Y => a11);
I_11a : std_buf_22 port map( IN0 => a11, Y => a12);
I_1a : std_buf_21 port map( IN0 => a1, Y => a2);
end SYN_gcd_fab4_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_gout_tempvar is
port( din : in std_logic_vector (0 to 7); latch : in std_logic; dout : out
std_logic_vector (0 to 7));
end gcd_gout_tempvar;
architecture SYN_gcd_gout_tempvar_behv of gcd_gout_tempvar is
component stddff
port( CLK, D : in std_logic; Q : out std_logic);
end component;
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal n36 : std_logic;
begin
U8 : stdbuf_2x port map( IN0 => latch, Y => n36);
dout_reg_0 : stddff port map( CLK => n36, D => din(7), Q => dout(7));
dout_reg_1 : stddff port map( CLK => n36, D => din(6), Q => dout(6));
dout_reg_2 : stddff port map( CLK => n36, D => din(5), Q => dout(5));
dout_reg_3 : stddff port map( CLK => n36, D => din(4), Q => dout(4));
dout_reg_4 : stddff port map( CLK => n36, D => din(3), Q => dout(3));
dout_reg_5 : stddff port map( CLK => n36, D => din(2), Q => dout(2));
dout_reg_6 : stddff port map( CLK => n36, D => din(1), Q => dout(1));
dout_reg_7 : stddff port map( CLK => n36, D => din(0), Q => dout(0));
end SYN_gcd_gout_tempvar_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab4_DW01_sub_8_0 is
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; DIFF : out
std_logic_vector (0 to 7); CO : out std_logic);
end gcd_fab4_DW01_sub_8_0;
architecture SYN_rpl of gcd_fab4_DW01_sub_8_0 is
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdxnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdadd2
port( A, B, CIN : in std_logic; COUT, Y : out std_logic);
end component;
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal X_cell_57_carry_7, X_cell_57_carry_6, X_cell_57_carry_5,
X_cell_57_carry_4, X_cell_57_carry_3, X_cell_57_carry_2,
X_cell_57_carry_1, X_cell_57_B_not_7, X_cell_57_B_not_6,
X_cell_57_B_not_5, X_cell_57_B_not_4, X_cell_57_B_not_3,
X_cell_57_B_not_2, X_cell_57_B_not_1, X_cell_57_B_not_0 : std_logic;
begin
U7 : stdbufinv port map( IN0 => B(5), Y => X_cell_57_B_not_2);
U8 : stdbufinv port map( IN0 => B(4), Y => X_cell_57_B_not_3);
U9 : stdbufinv port map( IN0 => B(3), Y => X_cell_57_B_not_4);
U10 : stdbufinv port map( IN0 => B(2), Y => X_cell_57_B_not_5);
U11 : stdbufinv port map( IN0 => B(1), Y => X_cell_57_B_not_6);
U12 : stdbufinv port map( IN0 => B(0), Y => X_cell_57_B_not_7);
U13 : stdadd2 port map( A => A(5), B => X_cell_57_B_not_2, CIN =>
X_cell_57_carry_2, COUT => X_cell_57_carry_3, Y =>
DIFF(5));
U14 : stdadd2 port map( A => A(6), B => X_cell_57_B_not_1, CIN =>
X_cell_57_carry_1, COUT => X_cell_57_carry_2, Y =>
DIFF(6));
U15 : stdadd2 port map( A => A(0), B => X_cell_57_B_not_7, CIN =>
X_cell_57_carry_7, COUT => open, Y => DIFF(0));
U16 : stdadd2 port map( A => A(1), B => X_cell_57_B_not_6, CIN =>
X_cell_57_carry_6, COUT => X_cell_57_carry_7, Y =>
DIFF(1));
U17 : stdadd2 port map( A => A(2), B => X_cell_57_B_not_5, CIN =>
X_cell_57_carry_5, COUT => X_cell_57_carry_6, Y =>
DIFF(2));
U18 : stdadd2 port map( A => A(3), B => X_cell_57_B_not_4, CIN =>
X_cell_57_carry_4, COUT => X_cell_57_carry_5, Y =>
DIFF(3));
U19 : stdadd2 port map( A => A(4), B => X_cell_57_B_not_3, CIN =>
X_cell_57_carry_3, COUT => X_cell_57_carry_4, Y =>
DIFF(4));
U3 : stdor2 port map( IN0 => A(7), IN1 => X_cell_57_B_not_0, Y =>
X_cell_57_carry_1);
U4 : stdxnor2 port map( IN0 => X_cell_57_B_not_0, IN1 => A(7), Y => DIFF(7))
;
U5 : stdbufinv port map( IN0 => B(7), Y => X_cell_57_B_not_0);
U6 : stdbufinv port map( IN0 => B(6), Y => X_cell_57_B_not_1);
end SYN_rpl;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab4 is
port( y, x : in std_logic_vector (0 to 7); y_out : out std_logic_vector (0
to 7));
end gcd_fab4;
architecture SYN_gcd_fab4beh of gcd_fab4 is
component gcd_fab4_DW01_sub_8_0
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; DIFF :
out std_logic_vector (0 to 7); CO : out std_logic);
end component;
signal n67 : std_logic;
begin
sub_14_minus_minus : gcd_fab4_DW01_sub_8_0 port map( A(0) => y(0), A(1) =>
y(1), A(2) => y(2), A(3) => y(3), A(4) => y(4), A(5)
=> y(5), A(6) => y(6), A(7) => y(7), B(0) => x(0),
B(1) => x(1), B(2) => x(2), B(3) => x(3), B(4) =>
x(4), B(5) => x(5), B(6) => x(6), B(7) => x(7), CI
=> n67, DIFF(0) => y_out(0), DIFF(1) => y_out(1),
DIFF(2) => y_out(2), DIFF(3) => y_out(3), DIFF(4) =>
y_out(4), DIFF(5) => y_out(5), DIFF(6) => y_out(6),
DIFF(7) => y_out(7), CO => open);
n67 <= '0';
end SYN_gcd_fab4beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdor2b_1 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdor2b_1;
architecture SYN_stdor2b_behv_1 of stdor2b_1 is
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdor2 port map( IN0 => IN1, IN1 => IN0, Y => Y);
end SYN_stdor2b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_1 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_1;
architecture SYN_stdnand2b_behv_1 of stdnand2b_1 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_3 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_3;
architecture SYN_stdbufinvb_behv_3 of stdbufinvb_3 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_1 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_1;
architecture SYN_stdand2b_behv_1 of stdand2b_1 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_2 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_2;
architecture SYN_stdoaoi211b_behv_2 of stdoaoi211b_2 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoa21b is
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end stdoa21b;
architecture SYN_stdoa21b_behv of stdoa21b is
component stdoai21
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoai21 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, Y => Y);
end SYN_stdoa21b_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi21b is
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end stdaoi21b;
architecture SYN_stdaoi21b_behv of stdaoi21b is
component stdaoi21
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi21 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, Y => Y);
end SYN_stdaoi21b_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi22b_2 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi22b_2;
architecture SYN_stdaoi22b_behv_2 of stdaoi22b_2 is
component stdaoi22
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi22 port map( IN0 => IN2, IN1 => IN3, IN2 => IN0, IN3 => IN1, Y =>
Y);
end SYN_stdaoi22b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_2 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_2;
architecture SYN_stdnor2b_behv_2 of stdnor2b_2 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_1 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_1;
architecture SYN_stdnor2b_behv_1 of stdnor2b_1 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdor2b_2 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdor2b_2;
architecture SYN_stdor2b_behv_2 of stdor2b_2 is
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdor2 port map( IN0 => IN1, IN1 => IN0, Y => Y);
end SYN_stdor2b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_x_loaddone_ism is
port( RESET, xldd, sel1t, sel0t : in std_logic; gcdxldd, processxldd : out
std_logic);
end gcd_x_loaddone_ism;
architecture SYN_gcd_x_loaddone_ism_behv of gcd_x_loaddone_ism is
component stdor2b_1
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_1
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_3
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_1
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_2
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdoa21b
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end component;
component stdaoi21b
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end component;
component stdaoi22b_2
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_1
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdor2b_2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
signal Pa00_z, node_534_z, n1, node_47_z, Ya_i, node_537_z, node_538_z,
node_49_z, node_595_z, node_41_z, node_532_z : std_logic;
begin
U_0 : stdbufinvb_3 port map( IN0 => n1, Y => node_532_z);
U_1 : stdnor2b_2 port map( IN0 => node_532_z, IN1 => sel1t, Y => node_534_z)
;
U_2 : stdnand2b_1 port map( IN0 => sel1t, IN1 => node_532_z, Y => node_47_z)
;
U_3 : stdor2b_2 port map( IN0 => Ya_i, IN1 => sel0t, Y => Pa00_z);
U_4 : stdoa21b port map( IN0 => xldd, IN1 => node_47_z, IN2 => Pa00_z, Y =>
node_49_z);
U_5 : stdaoi21b port map( IN0 => xldd, IN1 => node_534_z, IN2 => node_49_z,
Y => node_595_z);
U_6 : stdnor2b_1 port map( IN0 => node_595_z, IN1 => RESET, Y => gcdxldd);
U_7 : stdor2b_1 port map( IN0 => Ya_i, IN1 => sel0t, Y => node_41_z);
U_8 : stdand2b_1 port map( IN0 => Ya_i, IN1 => sel0t, Y => node_537_z);
U_9 : stdaoi22b_2 port map( IN0 => sel1t, IN1 => node_532_z, IN2 => xldd,
IN3 => node_537_z, Y => node_538_z);
U_10 : stdoaoi211b_2 port map( IN0 => xldd, IN1 => node_41_z, IN2 =>
node_538_z, IN3 => RESET, Y => processxldd);
Ya_i <= '0';
n1 <= '0';
end SYN_gcd_x_loaddone_ism_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab3_DW01_sub_8_0 is
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; DIFF : out
std_logic_vector (0 to 7); CO : out std_logic);
end gcd_fab3_DW01_sub_8_0;
architecture SYN_rpl_architecture of gcd_fab3_DW01_sub_8_0 is
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdxnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdadd2
port( A, B, CIN : in std_logic; COUT, Y : out std_logic);
end component;
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal B_not_7, carry_1, carry_2, carry_3, carry_4, carry_5, carry_6,
carry_7, B_not_0, B_not_1, B_not_2, B_not_3, B_not_4, B_not_5, B_not_6 :
std_logic;
begin
U7 : stdbufinv port map( IN0 => B(5), Y => B_not_2);
U8 : stdbufinv port map( IN0 => B(4), Y => B_not_3);
U9 : stdbufinv port map( IN0 => B(3), Y => B_not_4);
sub_14_minus_minus_U2_7 : stdadd2 port map( A => A(0), B => B_not_7, CIN =>
carry_7, COUT => open, Y => DIFF(0));
sub_14_minus_minus_U2_6 : stdadd2 port map( A => A(1), B => B_not_6, CIN =>
carry_6, COUT => carry_7, Y => DIFF(1));
sub_14_minus_minus_U2_5 : stdadd2 port map( A => A(2), B => B_not_5, CIN =>
carry_5, COUT => carry_6, Y => DIFF(2));
sub_14_minus_minus_U2_4 : stdadd2 port map( A => A(3), B => B_not_4, CIN =>
carry_4, COUT => carry_5, Y => DIFF(3));
sub_14_minus_minus_U2_3 : stdadd2 port map( A => A(4), B => B_not_3, CIN =>
carry_3, COUT => carry_4, Y => DIFF(4));
sub_14_minus_minus_U2_2 : stdadd2 port map( A => A(5), B => B_not_2, CIN =>
carry_2, COUT => carry_3, Y => DIFF(5));
sub_14_minus_minus_U2_1 : stdadd2 port map( A => A(6), B => B_not_1, CIN =>
carry_1, COUT => carry_2, Y => DIFF(6));
U10 : stdbufinv port map( IN0 => B(2), Y => B_not_5);
U11 : stdbufinv port map( IN0 => B(1), Y => B_not_6);
U12 : stdbufinv port map( IN0 => B(0), Y => B_not_7);
U3 : stdor2 port map( IN0 => A(7), IN1 => B_not_0, Y => carry_1);
U4 : stdxnor2 port map( IN0 => B_not_0, IN1 => A(7), Y => DIFF(7));
U5 : stdbufinv port map( IN0 => B(7), Y => B_not_0);
U6 : stdbufinv port map( IN0 => B(6), Y => B_not_1);
end SYN_rpl_architecture;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab3 is
port( x, y : in std_logic_vector (0 to 7); x_out : out std_logic_vector (0
to 7));
end gcd_fab3;
architecture SYN_gcd_fab3beh of gcd_fab3 is
component gcd_fab3_DW01_sub_8_0
port( A, B : in std_logic_vector (0 to 7); CI : in std_logic; DIFF :
out std_logic_vector (0 to 7); CO : out std_logic);
end component;
signal n68 : std_logic;
begin
sub_14_minus_minus : gcd_fab3_DW01_sub_8_0 port map( A(0) => x(0), A(1) =>
x(1), A(2) => x(2), A(3) => x(3), A(4) => x(4), A(5)
=> x(5), A(6) => x(6), A(7) => x(7), B(0) => y(0),
B(1) => y(1), B(2) => y(2), B(3) => y(3), B(4) =>
y(4), B(5) => y(5), B(6) => y(6), B(7) => y(7), CI
=> n68, DIFF(0) => x_out(0), DIFF(1) => x_out(1),
DIFF(2) => x_out(2), DIFF(3) => x_out(3), DIFF(4) =>
x_out(4), DIFF(5) => x_out(5), DIFF(6) => x_out(6),
DIFF(7) => x_out(7), CO => open);
n68 <= '0';
end SYN_gcd_fab3beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_pab0 is
port( x, y : in std_logic_vector (0 to 7); select0_select : out std_logic);
end gcd_pab0;
architecture SYN_gcd_pab0beh of gcd_pab0 is
component stdnor4
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdand4
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
signal n98, n100, n99, n101 : std_logic;
begin
U10 : stdand4 port map( IN0 => n98, IN1 => n99, IN2 => n100, IN3 => n101, Y
=> select0_select);
U11 : stdnor4 port map( IN0 => y(0), IN1 => y(1), IN2 => y(2), IN3 => y(3),
Y => n101);
U12 : stdnor4 port map( IN0 => y(4), IN1 => y(5), IN2 => y(6), IN3 => y(7),
Y => n100);
U13 : stdnor4 port map( IN0 => x(0), IN1 => x(1), IN2 => x(2), IN3 => x(3),
Y => n99);
U14 : stdnor4 port map( IN0 => x(4), IN1 => x(5), IN2 => x(6), IN3 => x(7),
Y => n98);
end SYN_gcd_pab0beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_pab1_DW01_cmp2_8_0 is
port( A, B : in std_logic_vector (0 to 7); LEQ, TC : in std_logic; LT_LE,
GE_GT : out std_logic);
end gcd_pab1_DW01_cmp2_8_0;
architecture SYN_rpl_architecture2 of gcd_pab1_DW01_cmp2_8_0 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdoai32
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
component stdaoi21
port( IN0, IN1, IN2 : in std_logic; Y : out std_logic);
end component;
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi32
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
component stdoai22
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi222
port( IN0, IN1, IN2, IN3, IN4, IN5 : in std_logic; Y : out std_logic);
end component;
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal n19, n30, n31, n32, n20, n33, n21, n34, n22, n23, n24, n25, n26, n27,
n15, n28, n16, n29, n17, n18 : std_logic;
begin
U7 : stdand2 port map( IN0 => n18, IN1 => A(0), Y => n15);
U8 : stdaoi32 port map( IN0 => n28, IN1 => n29, IN2 => n30, IN3 => B(5), IN4
=> n31, Y => n21);
U9 : stdaoi21 port map( IN0 => B(3), IN1 => n32, IN2 => n19, Y => n26);
U20 : stdbufinv port map( IN0 => A(3), Y => n32);
U21 : stdbufinv port map( IN0 => B(2), Y => n25);
U22 : stdbufinv port map( IN0 => B(1), Y => n24);
U10 : stdoai22 port map( IN0 => A(7), IN1 => n33, IN2 => A(6), IN3 => n34, Y
=> n29);
U23 : stdbufinv port map( IN0 => B(7), Y => n33);
U11 : stdor2 port map( IN0 => n31, IN1 => B(5), Y => n28);
U12 : stdnand2 port map( IN0 => A(6), IN1 => n34, Y => n30);
U13 : stdor2 port map( IN0 => n20, IN1 => A(4), Y => n22);
U14 : stdor2 port map( IN0 => n25, IN1 => A(2), Y => n27);
U15 : stdbufinv port map( IN0 => B(0), Y => n18);
U16 : stdbufinv port map( IN0 => B(6), Y => n34);
U17 : stdbufinv port map( IN0 => A(5), Y => n31);
U18 : stdbufinv port map( IN0 => B(4), Y => n20);
U19 : stdbufinv port map( IN0 => B(3), Y => n23);
U3 : stdoai32 port map( IN0 => n15, IN1 => n16, IN2 => n17, IN3 => A(0), IN4
=> n18, Y => GE_GT);
U4 : stdaoi222 port map( IN0 => A(4), IN1 => n20, IN2 => n21, IN3 => n22,
IN4 => A(3), IN5 => n23, Y => n19);
U5 : stdnor2 port map( IN0 => A(1), IN1 => n24, Y => n16);
U6 : stdaoi222 port map( IN0 => A(2), IN1 => n25, IN2 => n26, IN3 => n27,
IN4 => A(1), IN5 => n24, Y => n17);
end SYN_rpl_architecture2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_pab1 is
port( x, y : in std_logic_vector (0 to 7); select1_select : out std_logic);
end gcd_pab1;
architecture SYN_gcd_pab1beh of gcd_pab1 is
component gcd_pab1_DW01_cmp2_8_0
port( A, B : in std_logic_vector (0 to 7); LEQ, TC : in std_logic;
LT_LE, GE_GT : out std_logic);
end component;
signal n76, n77 : std_logic;
begin
n76 <= '0';
n77 <= '1';
gte_17_geq_geq : gcd_pab1_DW01_cmp2_8_0 port map( A(0) => x(0), A(1) => x(1)
, A(2) => x(2), A(3) => x(3), A(4) => x(4), A(5) =>
x(5), A(6) => x(6), A(7) => x(7), B(0) => y(0), B(1)
=> y(1), B(2) => y(2), B(3) => y(3), B(4) => y(4),
B(5) => y(5), B(6) => y(6), B(7) => y(7), LEQ => n76
, TC => n77, LT_LE => open, GE_GT => select1_select)
;
end SYN_gcd_pab1beh;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_6 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_6;
architecture SYN_std_buf_behv_6 of std_buf_6 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_7 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_7;
architecture SYN_std_buf_behv_7 of std_buf_7 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_8 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_8;
architecture SYN_std_buf_behv_8 of std_buf_8 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_8;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_9 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_9;
architecture SYN_std_buf_behv_9 of std_buf_9 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_9;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_11 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_11;
architecture SYN_std_buf_behv_11 of std_buf_11 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_11;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_10 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_10;
architecture SYN_std_buf_behv_10 of std_buf_10 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_10;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_3 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_3;
architecture SYN_std_buf_behv_3 of std_buf_3 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_4 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_4;
architecture SYN_std_buf_behv_4 of std_buf_4 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_5 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_5;
architecture SYN_std_buf_behv_5 of std_buf_5 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_x_var_delay is
port( latch, x_loaddone : out std_logic; x_load : in std_logic);
end gcd_x_var_delay;
architecture SYN_gcd_x_var_delay_behv of gcd_x_var_delay is
component std_buf_6
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_7
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_8
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_9
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_11
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_10
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_3
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_4
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_5
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal l1, l2, a1, a2, a3, a4, a5 : std_logic;
begin
I_2a : std_buf_11 port map( IN0 => a2, Y => a3);
I_3a : std_buf_10 port map( IN0 => a3, Y => a4);
I_4a : std_buf_9 port map( IN0 => a4, Y => a5);
I_5a : std_buf_8 port map( IN0 => a5, Y => x_loaddone);
I_0 : std_buf_7 port map( IN0 => x_load, Y => l1);
I_1 : std_buf_6 port map( IN0 => x_load, Y => a1);
I_1l : std_buf_5 port map( IN0 => l1, Y => l2);
I_2l : std_buf_4 port map( IN0 => l2, Y => latch);
I_1a : std_buf_3 port map( IN0 => a1, Y => a2);
end SYN_gcd_x_var_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdor2b_0 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdor2b_0;
architecture SYN_stdor2b_behv_0 of stdor2b_0 is
component stdor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdor2 port map( IN0 => IN1, IN1 => IN0, Y => Y);
end SYN_stdor2b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_0 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_0;
architecture SYN_stdnand2b_behv_0 of stdnand2b_0 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_0 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_0;
architecture SYN_stdbufinvb_behv_0 of stdbufinvb_0 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_1 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_1;
architecture SYN_stdbufinvb_behv_1 of stdbufinvb_1 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_2 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_2;
architecture SYN_stdbufinvb_behv_2 of stdbufinvb_2 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_0 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_0;
architecture SYN_stdand2b_behv_0 of stdand2b_0 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_0 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_0;
architecture SYN_stdoaoi211b_behv_0 of stdoaoi211b_0 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_1 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_1;
architecture SYN_stdoaoi211b_behv_1 of stdoaoi211b_1 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi22b_1 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi22b_1;
architecture SYN_stdaoi22b_behv_1 of stdaoi22b_1 is
component stdaoi22
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi22 port map( IN0 => IN2, IN1 => IN3, IN2 => IN0, IN3 => IN1, Y =>
Y);
end SYN_stdaoi22b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi22b_0 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi22b_0;
architecture SYN_stdaoi22b_behv_0 of stdaoi22b_0 is
component stdaoi22
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi22 port map( IN0 => IN2, IN1 => IN3, IN2 => IN0, IN3 => IN1, Y =>
Y);
end SYN_stdaoi22b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_0 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_0;
architecture SYN_stdnor2b_behv_0 of stdnor2b_0 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_y_loaddone_ism is
port( RESET, yldd, sel1f, sel0t : in std_logic; gcdyldd, processyldd : out
std_logic);
end gcd_y_loaddone_ism;
architecture SYN_gcd_y_loaddone_ism_behv of gcd_y_loaddone_ism is
component stdor2b_0
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_0
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_0
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_1
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_2
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_0
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_0
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_1
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdaoi22b_1
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdaoi22b_0
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_0
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
signal node_534_z, node_535_z, n1, node_47_z, Ya_i, node_529_z, node_537_z,
node_538_z, node_530_z, node_41_z, node_532_z : std_logic;
begin
U_0 : stdbufinvb_2 port map( IN0 => n1, Y => node_532_z);
U_1 : stdnand2b_0 port map( IN0 => sel1f, IN1 => node_532_z, Y => node_47_z)
;
U_2 : stdbufinvb_1 port map( IN0 => Ya_i, Y => node_529_z);
U_3 : stdbufinvb_0 port map( IN0 => sel0t, Y => node_530_z);
U_4 : stdnor2b_0 port map( IN0 => node_532_z, IN1 => sel1f, Y => node_534_z)
;
U_5 : stdaoi22b_1 port map( IN0 => node_529_z, IN1 => node_530_z, IN2 =>
yldd, IN3 => node_534_z, Y => node_535_z);
U_6 : stdoaoi211b_1 port map( IN0 => yldd, IN1 => node_47_z, IN2 =>
node_535_z, IN3 => RESET, Y => gcdyldd);
U_7 : stdor2b_0 port map( IN0 => Ya_i, IN1 => sel0t, Y => node_41_z);
U_8 : stdand2b_0 port map( IN0 => Ya_i, IN1 => sel0t, Y => node_537_z);
U_9 : stdaoi22b_0 port map( IN0 => sel1f, IN1 => node_532_z, IN2 => yldd,
IN3 => node_537_z, Y => node_538_z);
U_10 : stdoaoi211b_0 port map( IN0 => yldd, IN1 => node_41_z, IN2 =>
node_538_z, IN3 => RESET, Y => processyldd);
Ya_i <= '0';
n1 <= '0';
end SYN_gcd_y_loaddone_ism_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_19 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_19;
architecture SYN_std_buf_behv_19 of std_buf_19 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_19;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_18 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_18;
architecture SYN_std_buf_behv_18 of std_buf_18 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_18;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_17 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_17;
architecture SYN_std_buf_behv_17 of std_buf_17 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_17;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_16 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_16;
architecture SYN_std_buf_behv_16 of std_buf_16 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_16;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_15 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_15;
architecture SYN_std_buf_behv_15 of std_buf_15 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_15;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_14 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_14;
architecture SYN_std_buf_behv_14 of std_buf_14 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_14;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_13 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_13;
architecture SYN_std_buf_behv_13 of std_buf_13 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_13;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_12 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_12;
architecture SYN_std_buf_behv_12 of std_buf_12 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_12;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_20 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_20;
architecture SYN_std_buf_behv_20 of std_buf_20 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_20;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_y_var_delay is
port( latch, y_loaddone : out std_logic; y_load : in std_logic);
end gcd_y_var_delay;
architecture SYN_gcd_y_var_delay_behv of gcd_y_var_delay is
component std_buf_19
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_18
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_17
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_16
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_15
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_14
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_13
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_12
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_20
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal l1, l2, a1, a2, a3, a4, a5 : std_logic;
begin
I_2a : std_buf_20 port map( IN0 => a2, Y => a3);
I_3a : std_buf_19 port map( IN0 => a3, Y => a4);
I_4a : std_buf_18 port map( IN0 => a4, Y => a5);
I_5a : std_buf_17 port map( IN0 => a5, Y => y_loaddone);
I_0 : std_buf_16 port map( IN0 => y_load, Y => l1);
I_1 : std_buf_15 port map( IN0 => y_load, Y => a1);
I_1l : std_buf_14 port map( IN0 => l1, Y => l2);
I_2l : std_buf_13 port map( IN0 => l2, Y => latch);
I_1a : std_buf_12 port map( IN0 => a1, Y => a2);
end SYN_gcd_y_var_delay_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_15 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_15;
architecture SYN_stdbufinvb_behv_15 of stdbufinvb_15 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_15;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_16 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_16;
architecture SYN_stdbufinvb_behv_16 of stdbufinvb_16 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_16;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_5 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_5;
architecture SYN_stdnand2b_behv_5 of stdnand2b_5 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_6 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_6;
architecture SYN_stdnand2b_behv_6 of stdnand2b_6 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_7 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_7;
architecture SYN_stdnand2b_behv_7 of stdnand2b_7 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_8 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_8;
architecture SYN_stdnand2b_behv_8 of stdnand2b_8 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_8;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_9 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_9;
architecture SYN_stdnand2b_behv_9 of stdnand2b_9 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_9;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_7 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_7;
architecture SYN_stdand2b_behv_7 of stdand2b_7 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_8 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_8;
architecture SYN_stdand2b_behv_8 of stdand2b_8 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_8;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_9 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_9;
architecture SYN_stdand2b_behv_9 of stdand2b_9 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_9;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_7 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_7;
architecture SYN_stdnor2b_behv_7 of stdnor2b_7 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi32b_2 is
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end stdaoi32b_2;
architecture SYN_stdaoi32b_behv_2 of stdaoi32b_2 is
component stdaoi32
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi32 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, IN4
=> IN4, Y => Y);
end SYN_stdaoi32b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_6 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_6;
architecture SYN_stdnor2b_behv_6 of stdnor2b_6 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi32b_1 is
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end stdaoi32b_1;
architecture SYN_stdaoi32b_behv_1 of stdaoi32b_1 is
component stdaoi32
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi32 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, IN4
=> IN4, Y => Y);
end SYN_stdaoi32b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_5 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_5;
architecture SYN_stdnor2b_behv_5 of stdnor2b_5 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi32b_0 is
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end stdaoi32b_0;
architecture SYN_stdaoi32b_behv_0 of stdaoi32b_0 is
component stdaoi32
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi32 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, IN4
=> IN4, Y => Y);
end SYN_stdaoi32b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_4 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_4;
architecture SYN_stdnor2b_behv_4 of stdnor2b_4 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnor2b_3 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnor2b_3;
architecture SYN_stdnor2b_behv_3 of stdnor2b_3 is
component stdnor2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnor2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnor2b_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi31b_2 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi31b_2;
architecture SYN_stdaoi31b_behv_2 of stdaoi31b_2 is
component stdaoi31
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi31 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, Y =>
Y);
end SYN_stdaoi31b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi31b_1 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi31b_1;
architecture SYN_stdaoi31b_behv_1 of stdaoi31b_1 is
component stdaoi31
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi31 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, Y =>
Y);
end SYN_stdaoi31b_behv_1;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdaoi31b_0 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdaoi31b_0;
architecture SYN_stdaoi31b_behv_0 of stdaoi31b_0 is
component stdaoi31
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdaoi31 port map( IN0 => IN1, IN1 => IN2, IN2 => IN0, IN3 => IN3, Y =>
Y);
end SYN_stdaoi31b_behv_0;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_12 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_12;
architecture SYN_stdnand2b_behv_12 of stdnand2b_12 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_12;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_11 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_11;
architecture SYN_stdnand2b_behv_11 of stdnand2b_11 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_11;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_10 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_10;
architecture SYN_stdnand2b_behv_10 of stdnand2b_10 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_10;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_11 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_11;
architecture SYN_stdbufinvb_behv_11 of stdbufinvb_11 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_11;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_12 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_12;
architecture SYN_stdbufinvb_behv_12 of stdbufinvb_12 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_12;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_13 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_13;
architecture SYN_stdbufinvb_behv_13 of stdbufinvb_13 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_13;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_14 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_14;
architecture SYN_stdbufinvb_behv_14 of stdbufinvb_14 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_14;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_gcd is
port( RESET, start, sel0t, sel0f, gouttvldd, gout0out, gcdyldd, gcdxldd,
gcdwhilereq, b2out, a1out : in std_logic; a1in2, b2in2, gout0in1,
gouttvld, processprocessreq, sel0req, xldx0, yldx0 : out std_logic);
end gcd_gcd;
architecture SYN_gcd_gcd_behv of gcd_gcd is
component stdbufinvb_15
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_16
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_5
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_6
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_7
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_8
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_9
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdand2b_7
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_8
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdand2b_9
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_7
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi32b_2
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_6
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi32b_1
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_5
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi32b_0
port( IN0, IN1, IN2, IN3, IN4 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_4
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnor2b_3
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdaoi31b_2
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdaoi31b_1
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdaoi31b_0
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_12
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_11
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_10
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_11
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_12
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_13
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_14
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal Pb00_z, Pa00_z, Pg00_z, Ph00_z, node_588_z, node_660_z, node_658_z,
Pg01_z, Ph01_z, node_589_z, n1, n3, Pg02_z, n4, Ph02_z, node_577_z,
node_594_z, node_592_z, node_584_z, node_591_z, node_585_z, Yf_i,
node_586_z, node_662_z : std_logic;
begin
U_0 : stdbufinvb_16 port map( IN0 => RESET, Y => node_577_z);
U_1 : stdnand2b_12 port map( IN0 => start, IN1 => node_577_z, Y => Pa00_z);
U_2 : stdnor2b_7 port map( IN0 => gout0out, IN1 => Pa00_z, Y => a1in2);
U_3 : stdnand2b_11 port map( IN0 => start, IN1 => node_577_z, Y => Pb00_z);
U_4 : stdnor2b_6 port map( IN0 => gout0out, IN1 => Pb00_z, Y => b2in2);
U_5 : stdand2b_9 port map( IN0 => gouttvldd, IN1 => node_577_z, Y =>
gout0in1);
U_6 : stdand2b_8 port map( IN0 => n4, IN1 => node_577_z, Y => n3);
U_7 : stdand2b_7 port map( IN0 => sel0f, IN1 => node_577_z, Y =>
processprocessreq);
U_8 : stdbufinvb_15 port map( IN0 => gcdwhilereq, Y => node_658_z);
U_9 : stdnor2b_5 port map( IN0 => gcdyldd, IN1 => gcdxldd, Y => node_584_z);
Yf_i <= '0';
U_19 : stdnand2b_10 port map( IN0 => b2out, IN1 => a1out, Y => Pg00_z);
U_18 : stdaoi31b_2 port map( IN0 => node_585_z, IN1 => node_589_z, IN2 =>
node_592_z, IN3 => RESET, Y => sel0req);
U_17 : stdaoi32b_2 port map( IN0 => node_662_z, IN1 => gcdxldd, IN2 =>
node_586_z, IN3 => gcdwhilereq, IN4 => node_591_z, Y
=> node_592_z);
U_16 : stdnor2b_4 port map( IN0 => gcdxldd, IN1 => Yf_i, Y => node_591_z);
U_15 : stdbufinvb_14 port map( IN0 => gcdwhilereq, Y => node_662_z);
U_14 : stdaoi32b_1 port map( IN0 => node_660_z, IN1 => gcdyldd, IN2 =>
node_586_z, IN3 => gcdwhilereq, IN4 => node_588_z, Y
=> node_589_z);
U_27 : stdaoi31b_1 port map( IN0 => Ph00_z, IN1 => Ph01_z, IN2 => Ph02_z,
IN3 => RESET, Y => yldx0);
U_13 : stdnor2b_3 port map( IN0 => gcdyldd, IN1 => Yf_i, Y => node_588_z);
U_26 : stdnand2b_9 port map( IN0 => b2out, IN1 => node_594_z, Y => Ph02_z);
U_25 : stdnand2b_8 port map( IN0 => a1out, IN1 => node_594_z, Y => Ph01_z);
U_12 : stdbufinvb_13 port map( IN0 => Yf_i, Y => node_586_z);
U_11 : stdbufinvb_12 port map( IN0 => gcdwhilereq, Y => node_660_z);
U_24 : stdnand2b_7 port map( IN0 => b2out, IN1 => a1out, Y => Ph00_z);
U_10 : stdaoi32b_0 port map( IN0 => node_658_z, IN1 => gcdyldd, IN2 =>
gcdxldd, IN3 => gcdwhilereq, IN4 => node_584_z, Y =>
node_585_z);
U_23 : stdaoi31b_0 port map( IN0 => Pg00_z, IN1 => Pg01_z, IN2 => Pg02_z,
IN3 => RESET, Y => xldx0);
U_22 : stdnand2b_6 port map( IN0 => b2out, IN1 => node_594_z, Y => Pg02_z);
U_21 : stdnand2b_5 port map( IN0 => a1out, IN1 => node_594_z, Y => Pg01_z);
U_20 : stdbufinvb_11 port map( IN0 => n1, Y => node_594_z);
n1 <= '0';
U2 : stdbuf port map( IN0 => sel0t, Y => n4);
U3 : stdbuf_2x port map( IN0 => n3, Y => gouttvld);
end SYN_gcd_gcd_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_2 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_2;
architecture SYN_stdnand2b_behv_2 of stdnand2b_2 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_3 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_3;
architecture SYN_stdnand2b_behv_3 of stdnand2b_3 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdnand2b_4 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdnand2b_4;
architecture SYN_stdnand2b_behv_4 of stdnand2b_4 is
component stdnand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdnand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdnand2b_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_4 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_4;
architecture SYN_stdbufinvb_behv_4 of stdbufinvb_4 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_2 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_2;
architecture SYN_stdand2b_behv_2 of stdand2b_2 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_2;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_5 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_5;
architecture SYN_stdbufinvb_behv_5 of stdbufinvb_5 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_6 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_6;
architecture SYN_stdbufinvb_behv_6 of stdbufinvb_6 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_3 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_3;
architecture SYN_stdand2b_behv_3 of stdand2b_3 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_7 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_7;
architecture SYN_stdbufinvb_behv_7 of stdbufinvb_7 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_7;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_4 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_4;
architecture SYN_stdand2b_behv_4 of stdand2b_4 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_8 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_8;
architecture SYN_stdbufinvb_behv_8 of stdbufinvb_8 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_8;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_5 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_5;
architecture SYN_stdand2b_behv_5 of stdand2b_5 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_9 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_9;
architecture SYN_stdbufinvb_behv_9 of stdbufinvb_9 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_9;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdand2b_6 is
port( IN0, IN1 : in std_logic; Y : out std_logic);
end stdand2b_6;
architecture SYN_stdand2b_behv_6 of stdand2b_6 is
component stdand2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdand2 port map( IN0 => IN0, IN1 => IN1, Y => Y);
end SYN_stdand2b_behv_6;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_3 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_3;
architecture SYN_stdoaoi211b_behv_3 of stdoaoi211b_3 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_3;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_4 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_4;
architecture SYN_stdoaoi211b_behv_4 of stdoaoi211b_4 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_4;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdoaoi211b_5 is
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end stdoaoi211b_5;
architecture SYN_stdoaoi211b_behv_5 of stdoaoi211b_5 is
component stdoaoi211
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdoaoi211 port map( IN0 => IN0, IN1 => IN1, IN2 => IN2, IN3 => IN3, Y
=> Y);
end SYN_stdoaoi211b_behv_5;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity stdbufinvb_10 is
port( IN0 : in std_logic; Y : out std_logic);
end stdbufinvb_10;
architecture SYN_stdbufinvb_behv_10 of stdbufinvb_10 is
component stdbufinv
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U2 : stdbufinv port map( IN0 => IN0, Y => Y);
end SYN_stdbufinvb_behv_10;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_process is
port( RESET, sel1t, sel1f, processyldd, processxldd, processprocessreq,
fab4ack, fab3ack : in std_logic; fab3req, fab4req, gcdwhilereq,
gcdxsm1, gcdysm1, sel1req, xldx1, yldx1 : out std_logic);
end gcd_process;
architecture SYN_gcd_process_behv of gcd_process is
component stdnand2b_2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_3
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdnand2b_4
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbuf_2x
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_4
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_2
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_5
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_6
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_3
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_7
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_4
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_8
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_5
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_9
port( IN0 : in std_logic; Y : out std_logic);
end component;
component stdand2b_6
port( IN0, IN1 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_3
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_4
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdoaoi211b_5
port( IN0, IN1, IN2, IN3 : in std_logic; Y : out std_logic);
end component;
component stdbufinvb_10
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal Pf00_z, Pd01_z, Pe01_z, n1, node_536_z, node_537_z, node_569_z,
node_538_z, node_541_z, node_565_z, node_574_z : std_logic;
begin
U_0 : stdbufinvb_10 port map( IN0 => RESET, Y => node_536_z);
U_1 : stdand2b_6 port map( IN0 => sel1t, IN1 => node_536_z, Y => fab3req);
U_2 : stdand2b_5 port map( IN0 => sel1f, IN1 => node_536_z, Y => fab4req);
U_3 : stdand2b_4 port map( IN0 => processyldd, IN1 => node_536_z, Y =>
gcdwhilereq);
U_4 : stdbufinvb_9 port map( IN0 => processxldd, Y => node_538_z);
U_5 : stdbufinvb_8 port map( IN0 => processxldd, Y => node_569_z);
U_6 : stdnand2b_4 port map( IN0 => fab3ack, IN1 => node_569_z, Y => Pd01_z);
U_7 : stdoaoi211b_5 port map( IN0 => node_538_z, IN1 => fab3ack, IN2 =>
Pd01_z, IN3 => RESET, Y => gcdxsm1);
U_8 : stdbufinvb_7 port map( IN0 => processyldd, Y => node_537_z);
U_9 : stdbufinvb_6 port map( IN0 => processyldd, Y => node_565_z);
U_17 : stdand2b_3 port map( IN0 => fab4ack, IN1 => node_536_z, Y => yldx1);
U_16 : stdand2b_2 port map( IN0 => fab3ack, IN1 => node_536_z, Y => xldx1);
U_15 : stdoaoi211b_4 port map( IN0 => node_541_z, IN1 => processxldd, IN2 =>
Pf00_z, IN3 => RESET, Y => sel1req);
U_14 : stdnand2b_3 port map( IN0 => processxldd, IN1 => node_574_z, Y =>
Pf00_z);
U_13 : stdbufinvb_5 port map( IN0 => processprocessreq, Y => node_574_z);
U_12 : stdbufinvb_4 port map( IN0 => processprocessreq, Y => node_541_z);
U_11 : stdoaoi211b_3 port map( IN0 => node_537_z, IN1 => fab4ack, IN2 =>
Pe01_z, IN3 => RESET, Y => n1);
U_10 : stdnand2b_2 port map( IN0 => fab4ack, IN1 => node_565_z, Y => Pe01_z)
;
U1 : stdbuf_2x port map( IN0 => n1, Y => gcdysm1);
end SYN_gcd_process_behv;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_68 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_68;
architecture SYN_std_buf_behv_68 of std_buf_68 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_68;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_67 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_67;
architecture SYN_std_buf_behv_67 of std_buf_67 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_67;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_66 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_66;
architecture SYN_std_buf_behv_66 of std_buf_66 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_66;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_79 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_79;
architecture SYN_std_buf_behv_79 of std_buf_79 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_79;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_65 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_65;
architecture SYN_std_buf_behv_65 of std_buf_65 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_65;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_78 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_78;
architecture SYN_std_buf_behv_78 of std_buf_78 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_78;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_64 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_64;
architecture SYN_std_buf_behv_64 of std_buf_64 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_64;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_77 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_77;
architecture SYN_std_buf_behv_77 of std_buf_77 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_77;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_63 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_63;
architecture SYN_std_buf_behv_63 of std_buf_63 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_63;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_76 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_76;
architecture SYN_std_buf_behv_76 of std_buf_76 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_76;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_62 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_62;
architecture SYN_std_buf_behv_62 of std_buf_62 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_62;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_75 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_75;
architecture SYN_std_buf_behv_75 of std_buf_75 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_75;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_61 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_61;
architecture SYN_std_buf_behv_61 of std_buf_61 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_61;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_74 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_74;
architecture SYN_std_buf_behv_74 of std_buf_74 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_74;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_73 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_73;
architecture SYN_std_buf_behv_73 of std_buf_73 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_73;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_60 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_60;
architecture SYN_std_buf_behv_60 of std_buf_60 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_60;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_72 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_72;
architecture SYN_std_buf_behv_72 of std_buf_72 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_72;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_71 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_71;
architecture SYN_std_buf_behv_71 of std_buf_71 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_71;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_70 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_70;
architecture SYN_std_buf_behv_70 of std_buf_70 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_70;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity std_buf_69 is
port( IN0 : in std_logic; Y : out std_logic);
end std_buf_69;
architecture SYN_std_buf_behv_69 of std_buf_69 is
component stdbuf
port( IN0 : in std_logic; Y : out std_logic);
end component;
begin
U1 : stdbuf port map( IN0 => IN0, Y => Y);
end SYN_std_buf_behv_69;
library IEEE;
library EPOCH_LIB;
use IEEE.std_logic_1164.ALL;
use EPOCH_LIB.components.ALL;
use work.CONV_PACK_gcd.all;
entity gcd_fab3_delay is
port( fab3_ack : out std_logic; fab3_req : in std_logic);
end gcd_fab3_delay;
architecture SYN_gcd_fab3_delay_behv of gcd_fab3_delay is
component std_buf_68
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_67
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_66
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_79
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_65
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_78
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_64
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_77
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_63
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_76
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_62
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_75
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_61
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_74
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_73
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_60
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_72
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_71
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_70
port( IN0 : in std_logic; Y : out std_logic);
end component;
component std_buf_69
port( IN0 : in std_logic; Y : out std_logic);
end component;
signal a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, a16
, a17, a18, a19 : std_logic;
begin
I_12a : std_buf_79 port map( IN0 => a12, Y => a13);
I_2a : std_buf_78 port map( IN0 => a2, Y => a3);
I_13a : std_buf_77 port map( IN0 => a13, Y => a14);
I_3a : std_buf_76 port map( IN0 => a3, Y => a4);
I_14a : std_buf_75 port map( IN0 => a14, Y => a15);
I_4a : std_buf_74 port map( IN0 => a4, Y => a5);
I_15a : std_buf_73 port map( IN0 => a15, Y => a16);
I_5a : std_buf_72 port map( IN0 => a5, Y => a6);
I_16a : std_buf_71 port map( IN0 => a16, Y => a17);
I_6a : std_buf_70 port map( IN0 => a6, Y => a7);
I_17a : std_buf_69 port map( IN0 => a17, Y => a18);
I_7a : std_buf_68 port map( IN0 => a7, Y => a8);
I_18a : std_buf_67 port map( IN0 => a18, Y => a19);
I_8a : std_buf_66 port map( IN0 => a8, Y => a9);
I_0 : std_buf_65 port map( IN0 => fab3_req, Y => a1);
I_19a : std_buf_64 port map( IN0 => a19, Y => fab3_ack);
I_9a : std_buf_63 port map( IN0 => a9, Y => a10);
I_10a : std_buf_62 port map( IN0 => a10, Y => a11);
I_11a : std_buf_61 port map( IN0 => a11, Y => a12);
I_1a : std_buf_60 port map( IN0 => a1, Y => a2);
end SYN_gcd_fab3_delay_behv;