ACK - An Asynchronous Design Framework

Control Synthesis


Burstmode Synthesis
 
             


Technology Mapping











Burstmode Graph

  =>  

a1in2 = gout0out' start 
b2in2 = gout0out' start 
gout0in1 = gouttvldd 
gouttvld = sel0t 
processreq = sel0f 
sel0req =
  gcdwr' gcdxldd gcdyldd +
  gcdwr gcdxldd' gcdyldd' +
  gcdwr' gcdxldd sel0req +
  gcdwr gcdxldd' sel0req +
  gcdwr' gcdyldd sel0req +
  gcdwr gcdyldd' sel0req 
xldx0 =
  a1out b2out +
  a1out yldx0 +
  b2out yldx0 
yldx0 =
  a1out b2out +
  a1out yldx0 +
  b2out yldx0 


Logic Equation

  =>  




Structural VHDL Gate Netlist