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The ACK system is built up of several public domain and also commercial design tools. The ACK system flow is shown in Figure 1 and is accompanied by a brief description of each step in the synthesis process. The shaded boxes indicates tools developed by us.

Figure 1: ACK System Flow

• Design specification - Two languages are supported for specifying the design to be synthesized. They are Verilog-+, a subset of Verilog extended to support channel communication, and HOP which is basically a high level Petri-net language. Behavioral simulation can then be performed in a Verilog simulator e.g. Veriwell.

• High Level Synthesis - If Verilog is chosen as input specification, then it is first translated into HOP. An Allocation and Refinement process is then performed on the Petri-net graph. This process consists of first allocating datapath resources such as library/ViewLogic-synthesized operators for computation, select blocks for data dependent choices, C-elements for channel communication, and library registers for storage. The underlying control graph is then obtained by refining each high level Petri-net action into two or four-phase handshaking actions acting on the allocated datapath resources.

• Partitioning - The refined control graph is now partitioned into sequential subgraphs for later synthesis to burst mode machines. The partitioning step has to solve non-trivial signal sharing dependencies due to the incompletely specified nature of the control graphs - a common problem in asynchronous design to which a general solution is given in our tool.

• Datapath synthesis - The allocated datapath resources are now synthesized using ViewLogic and then automatically interconnected.

• BurstMode generation - The refined and partitioned control graphs are now synthesized into Asynchronous Finite State Machines represented as burst mode machine descriptions.

• The burst mode machine descriptions can now be synthesized into either a standard gate implementation or a multilevel customized complex gate realization. A special technique called SOP/SOP form of complex CMOS gates which reduces the constraints for hazard free synthesis is introduced in our complex gate tool.

• If standard gates were chosen for the control implementation, the Lager layout tools are used to generate a layout for the design. If complex gates were chosen, a layout is generated by the Cadence LAS(TM) system.

• The layout is then extracted in Magic and a CIF file generated.

• The design can now be converted to any format supported by MOSIS and manufactured.