Datapath Synthesis (Synopsys)

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
 
entity gcd_pab1 is port(
  signal x : in std_logic_vector(7 downto 0);
  signal y : in std_logic_vector(7 downto 0);
  signal select1_select : out std_logic );
end gcd_pab1;

architecture gcd_pab1beh of gcd_pab1 is
begin 
  process(x,y)
  begin
    if (x >= y) then
      select1_select <= '1';
    else
      select1_select <= '0';
    end if;
  end process; 
end gcd_pab1beh;

  =>