Presentation of ACK

Important Features For High Level Asynchronous Circuit Design




Similar to synchronous methods

- Incorporate in standard synchronous framework

- Take advantage of synchronous research

Standard HDL

- Capture system structure rather than individual controllers

- Design portability, ease of use

- Behavioral simulation using available simulators

Target state machines

- Efficient implementations

- Complex synthesis

Partitioning

- Ability to synthesize large controllers

- Exploit temporal and spatial locality

Complex gate realization

- Where efficiency is critical

- Allow transistor sizing for speed/area/power tradeoff

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