Email: my first name @ cs.utah.edu
50 S. Central Campus Drive, Rm. 3414,
Salt Lake City, UT 84112
Ph: 801-581-4553; Fax: 801-581-5843
Detailed research page |
Full publication list |
Teaching page |
Utah Arch Research Group |
Recent Papers (Full list of publications) :
Other Selected Publications (Full list of publications) :
My research focuses on many aspects of computer architecture. I am
especially interested in studying how future technology trends
influence the design of microprocessors and memory systems. In recent
years, we have focused on designing memory systems that can cater to
the bandwidth, latency, power, cost, and reliability demands of
datacenter and big-data workloads.
Current projects include:
Past projects include:
- Memory Systems : optimizing DRAM/NVM chips, memory controllers, and data/computation placement for big-data and datacenter workloads.
- Reliability : efficient mechanisms to support chipkill reliability in the memory system.
- Large cache design : methodologies to model large NUCA cache hierarchies, policies to organize data, and organizations in 3D.
Multi-Core Cache Hierarchies , Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar, Synthesis Lectures in Computer Architecture , Morgan and Claypool Publishers, 2011.
( CACTI mirror site )
I typically teach CS 7810 Advanced Computer Architecture,
CS 6810 Computer Architecture,
CS 3810 Computer Organization,
and the Architecture/VLSI Seminar (CS 7937).
Courses taught in the past are listed here.
In Fall 2015, I'm teaching CS/ECE 3810,
and the Architecture/VLSI Seminar . In Spring 2016, I'm teaching CS/ECE 6810, and the Architecture/VLSI Seminar .
- Naveen Muralimanohar , Ph.D. September 2008, Wire-Aware Cache Architectures , First employment: HP Labs.
- Niti Madan , Ph.D. January 2009, Leveraging Mixed-process 3D Die Stacking Technology for Cache Hierarchies and Reliability , First employment: Computing Innovation Fellow at IBM T.J. Watson, Current employment: Oracle.
- Manu Awasthi , Ph.D. September 2011, Managing Data Locality in Future Memory Hierarchies Using a Hardware Software Co-Design Approach , First employment: Micron, Current employment: Samsung.
- Aniruddha Udipi , Ph.D. March 2012, Designing Efficient Memory for Future Computing Systems , First employment: ARM, Current employment: Google.
- Kshitij Sudan , Ph.D. October 2012, Data Placement for Efficient Main Memory Access , First employment: Samsung, Current employment: ARM.
- Niladrish Chatterjee , Ph.D. September 2013, Designing Efficient Memory Schedulers for Future Systems , First employment: NVidia.
- Seth Pugsley , Ph.D. May 2014, Opportunities for Near Data Computing in MapReduce Workloads , First employment: Intel.
- Manju Shevgoor , Ph.D. October 2015, Enabling Big Memory with Emerging Technologies, First employment: Intel.
- Vivek Venkatesan , M.S. December 2007, Criticality of On-Chip Wires , First employment: Sun (currently, Oracle).
- Byong Wu Chong, M.S. December 2012, Transactional Memory , First employment: Broadcom.
- Gita Sreekumar, M.S. December 2014, First employment: Qualtrics.
- Sahil Koladiya, M.S. May 2015, First employment: Cisco.
- Akhila Gundu, M.S. May 2015, First employment: Micron.
- Ali Shafiee , Ph.D. student, Machine Learning Accelerators
- Meysam Taassori, Ph.D. student, DRAM Variation
- Arjun Deb, MS student, Near Data Processing
- Karl Taht, Ph.D. student, Prefetching
- Anirban Nag, Ph.D. student, Machine Learning Accelerators
- Surya Narayanan, Ph.D. student, Neuromorphic Architectures
- Chandru Nagarajan, MS student, Neuromorphic Architectures
Life outside work
My blood pressure as an Assistant Professor was 30 points lower than what
it was as a grad student. Must have something to do with a
and a wonderful sport.
And now, the newest distractions: Shurik